diff --git a/arch/at91sam3x8e/sys.c b/arch/at91sam3x8e/sys.c
index b0ab432..ce95737 100644
--- a/arch/at91sam3x8e/sys.c
+++ b/arch/at91sam3x8e/sys.c
@@ -21,10 +21,6 @@ int sys_init(void)
 	REG_EEFC0_FMR = REG_EEFC_FWS_VAL(4);
 	REG_EEFC1_FMR = REG_EEFC_FWS_VAL(4);
 
-	/* disable osc write protection */
-	REG_PMC_WPMR = REG_PMC_WPMR_WPKEY_VAL(REG_PMC_WPMR_WPKEY_MAGIC)
-		     & ~REG_PMC_WPMR_WPEN_BIT;
-
 	/*
 	 * 1. Enabling the Main Oscillator
 	 */
@@ -44,7 +40,7 @@ int sys_init(void)
 		     | REG_CKGR_MOR_MOSCRCEN_BIT
 		     | REG_CKGR_MOR_MOSCXTEN_BIT
 		     | REG_CKGR_MOR_MOSCSEL_BIT;
-	mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MOSCXTS_BIT);
+	mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MOSCSELS_BIT);
 
 	REG_PMC_MCKR = (REG_PMC_MCKR & ~REG_PMC_MCKR_CSS_MASK)
 		     | REG_PMC_MCKR_CSS_VAL(1 /* = main clock */);
@@ -79,9 +75,6 @@ int sys_init(void)
 		     | REG_PMC_MCKR_CSS_VAL(2 /* = PLLA clock */);
 	mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MCKRDY_BIT);
 
-	/* turn osc write protection on again */
-	REG_PMC_WPMR |= REG_PMC_WPMR_WPEN_BIT;
-
 	sys_core_clock = 84000000UL;
 	return 0;
 }
diff --git a/include/arch/at91sam3x8e/hardware.h b/include/arch/at91sam3x8e/hardware.h
index 0e150d5..43f1c72 100644
--- a/include/arch/at91sam3x8e/hardware.h
+++ b/include/arch/at91sam3x8e/hardware.h
@@ -339,8 +339,38 @@ struct reg_snapshot {
 /** UART Receiver Holding Register */
 #define REG_UART_THR			(*(uint8_t *)0x400E081CU)
 
+/** UART Baud Rate Generator Register */
 #define REG_UART_BRGR			(*(uint16_t *)0x400E0820U)
 
+/* UART PDC Area */
+
+/** UART PDC Receive Pointer Register */
+#define REG_UART_PDC_RPR		(*(uint32_t *)0x400E0900U)
+/** UART PDC Receive Counter Register */
+#define REG_UART_PDC_RCR		(*(uint32_t *)0x400E0904U)
+/** UART PDC Transmit Pointer Register */
+#define REG_UART_PDC_TPR		(*(uint32_t *)0x400E0908U)
+/** UART PDC Transmit Counter Register */
+#define REG_UART_PDC_TCR		(*(uint32_t *)0x400E090CU)
+/** UART PDC Receive Next Pointer Register */
+#define REG_UART_PDC_RNPR		(*(uint32_t *)0x400E0910U)
+/** UART PDC Receive Next Counter Register */
+#define REG_UART_PDC_RNCR		(*(uint32_t *)0x400E0914U)
+/** UART PDC Transmit Next Pointer Register */
+#define REG_UART_PDC_TNPR		(*(uint32_t *)0x400E0918U)
+/** UART PDC Transmit Next Counter Register */
+#define REG_UART_PDC_TNCR		(*(uint32_t *)0x400E091CU)
+
+/** UART PDC Transfer Control Register */
+#define REG_UART_PDC_PTCR		(*(uint32_t *)0x400E0920U)
+#define REG_UART_PDC_PTCR_TXTDIS_MASK	((uint32_t)1 << 9)
+#define REG_UART_PDC_PTCR_TXTEN_MASK	((uint32_t)1 << 8)
+#define REG_UART_PDC_PTCR_RXTDIS_MASK	((uint32_t)1 << 1)
+#define REG_UART_PDC_PTCR_RXTEN_MASK	((uint32_t)1 << 0)
+
+/** UART PDC Transfer Status Register */
+#define REG_UART_PDC_PTSR		(*(uint32_t *)(0x400E0800U + 0x124C))
+
 /*
  * Nested Vectored Interrupt Controller
  */
@@ -655,13 +685,8 @@ struct reg_snapshot {
 
 /** PMC Write Protect Mode Register */
 #define REG_PMC_WPMR			(*(uint32_t *)0x400E06E4U)
-/** PMC Write Protect Key bitmask (<< 8, 24 bits, needs to be `0x504D43` ("PMC")) */
-#define REG_PMC_WPMR_WPKEY_MASK		((uint32_t)0xFFFFFF << 8)
-#define REG_PMC_WPMR_WPKEY_VAL(x) \
-	( ((uint32_t)(x) << 8) & REG_PMC_WPMR_WPKEY_MASK )
-#define REG_PMC_WPMR_WPKEY_MAGIC	(0x504D43) /* "PMC" in ASCII */
-/** PMC Write Protect Enable bitmask */
-#define REG_PMC_WPMR_WPEN_BIT		((uint32_t)1)
+#define REG_PMC_WPMR_WPKEY_MAGIC	(0x504D43 << 8) /* "PMC" in ASCII */
+#define REG_PMC_WPMR_WPEN_VAL(x)	((uint32_t)(x) | REG_PMC_WPMR_WPKEY_MAGIC)
 
 /** PMC Write Protect Status Register */
 #define REG_PMC_WPSR			(*(uint32_t *)0x400E06E8U)