100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/* See the end of this file for copyright, license, and warranty information. */
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#include <arch/interrupt.h>
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#include <arch/hardware.h>
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#include <arch-generic/hardware.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <string.h>
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#include <toolchain.h>
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/*
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* The initial sys_core_clock on system boot would actually be 4000000 because
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* the 4 MHz RC oscillator is used by default. However, for performance
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* reasons, the system core clock is configured to use the 84 MHz PLLA clock
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* even before the memory area for global variables (like this one) is copied
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* from flash to RAM, which in turn would overwrite any updates to the clock.
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* So, since we trust the clock to be configured correctly before this global
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* variable is accessed anywhere, we initialize it to the 84 MHz clock.
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*/
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uint32_t sys_core_clock = 84000000UL;
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void sys_init(void)
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{
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/*
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* This method is basically an implementation of chapter 28.12 in the
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* Atmel SAM3X8E Datasheet, combined with the startup code from libsam.
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*/
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/* # of wait states as per hardware spec (stolen from SAM SysInit) */
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REG_EEFC0_FMR = REG_EEFC_FWS_VAL(4);
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REG_EEFC1_FMR = REG_EEFC_FWS_VAL(4);
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/*
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* 1. Enabling the Main Oscillator
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*/
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/* initialize main osc */
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if (!(REG_CKGR_MOR & REG_CKGR_MOR_MOSCSEL_BIT)) {
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REG_CKGR_MOR = REG_CKGR_MOR_KEY_VAL(REG_CKGR_MOR_KEY_MAGIC)
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| REG_CKGR_MOR_MOSCXTST_VAL(8)
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| REG_CKGR_MOR_MOSCRCEN_BIT
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| REG_CKGR_MOR_MOSCXTEN_BIT;
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MOSCXTS_BIT);
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}
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/* switch to Xtal osc */
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REG_CKGR_MOR = REG_CKGR_MOR_KEY_VAL(REG_CKGR_MOR_KEY_MAGIC)
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| REG_CKGR_MOR_MOSCXTST_VAL(8)
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| REG_CKGR_MOR_MOSCRCEN_BIT
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| REG_CKGR_MOR_MOSCXTEN_BIT
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| REG_CKGR_MOR_MOSCSEL_BIT;
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MOSCSELS_BIT);
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REG_PMC_MCKR = (REG_PMC_MCKR & ~REG_PMC_MCKR_CSS_MASK)
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| REG_PMC_MCKR_CSS_VAL(1 /* = main clock */);
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MCKRDY_BIT);
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/*
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* 2. Checking the Main Oscillator Frequency (Optional)
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*/
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/* I repeat: **(Optional)** */
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/*
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* 3. Setting PLL and Divider
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*/
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REG_CKGR_PLLAR = REG_CKGR_PLLAR_ONE_BIT
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| REG_CKGR_PLLAR_MULA_VAL(0xD)
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| REG_CKGR_PLLAR_PLLACOUNT_VAL(0x3F /* maximum value */)
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| REG_CKGR_PLLAR_DIVA_VAL(0x1);
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_LOCKA_BIT);
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/*
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* 4. Selection of Master Clock and Processor Clock
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*/
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REG_PMC_MCKR = REG_PMC_MCKR_PRES_VAL(1 /* = as fast as it gets */)
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| REG_PMC_MCKR_CSS_VAL(1 /* = main clock */);
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MCKRDY_BIT);
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/* PMC_MCKR must not be configured within one clock cycle */
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REG_PMC_MCKR = REG_PMC_MCKR_PRES_VAL(1 /* = as fast as it gets */)
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| REG_PMC_MCKR_CSS_VAL(2 /* = PLLA clock */);
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MCKRDY_BIT);
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}
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/*
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* This file is part of Ardix.
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* Copyright (c) 2020, 2021 Felix Kopp <owo@fef.moe>.
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*
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* Ardix is non-violent software: you may only use, redistribute,
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* and/or modify it under the terms of the CNPLv6+ as found in
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* the LICENSE file in the source code root directory or at
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* <https://git.pixie.town/thufie/CNPL>.
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*
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* Ardix comes with ABSOLUTELY NO WARRANTY, to the extent
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* permitted by applicable law. See the CNPLv6+ for details.
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*/
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