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Finish an editing pass. A couple of issues remain:

Browse source 
- As noted in a comment, one entry refers to a load of nonexistent man
  pages, with no explanation of what they do.
- We are a bit inconsistent about the use of <tt> for command names.
- There is some duplication between the ThunderX and ARM64 status reports.
This commit is contained in:
David Chisnall 2015-10-22 13:18:05 +00:00
parent 91e4c306d0
commit 02f98a9e3e
Notes: svn2git 2020-12-08 03:00:23 +00:00 
svn path=/head/; revision=47638
1 changed files with 14 additions and 11 deletions
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en_US.ISO8859-1/htdocs/news/status/report-2015-07-2015-09.xml
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@ -123,7 +123,7 @@
transparent; applications must be adapted to take advantage of transparent; applications must be adapted to take advantage of
the hardware.</p> the hardware.</p>
<p>Some I/OAT models support more advanced copying modes, like <p>Some I/OAT models support more advanced copying modes, such as
XOR; these modes are not yet supported in the <tt>ioat(4)</tt> XOR; these modes are not yet supported in the <tt>ioat(4)</tt>
driver.</p> driver.</p>
</body> </body>
@ -273,6 +273,9 @@
boot process and keyboard driver as well as the boot process and keyboard driver as well as the
<tt>smbus(4)</tt> driver. It added three new drivers: <tt>smbus(4)</tt> driver. It added three new drivers:
<tt>ig4(4)</tt>, <tt>cyapa(4)</tt>, and <tt>isl(4)</tt>.</p> <tt>ig4(4)</tt>, <tt>cyapa(4)</tt>, and <tt>isl(4)</tt>.</p>
<!-- None of these drivers have man pages (at least, not indexed by the
web man page thing), so how is the reader expected to know what
they do or why they should care? -->
<p>Much of the development was originally done in late 2014. <p>Much of the development was originally done in late 2014.
Since then, the patches have been massively improved and Since then, the patches have been massively improved and
@ -888,8 +891,8 @@
ports received a major overhaul to make sure all ports are ports received a major overhaul to make sure all ports are
correctly configured. Dual version support was removed. correctly configured. Dual version support was removed.
There is only one mesa version for all supported &os; There is only one mesa version for all supported &os;
versions. The libosmesa port was merged into the Mesa versions. The libosmesa port, which provided the off-screen version of
framework.</p> Mesa, was merged into the Mesa framework.</p>
<p>Another big item that was included in the Mesa port is <p>Another big item that was included in the Mesa port is
OpenCL. There are two GPU-based OpenCL implementations: OpenCL. There are two GPU-based OpenCL implementations:
@ -1239,7 +1242,7 @@
<help> <help>
<task> <task>
<p>The GNOME website is stale. Work is under way to improve <p>The &os; GNOME website is stale. Work is under way to improve
it.</p> it.</p>
</task> </task>
@ -1307,16 +1310,16 @@
specifies the possible effects on memory of out-of-order and specifies the possible effects on memory of out-of-order and
speculative execution. More precisely, it specifies the speculative execution. More precisely, it specifies the
extent to which the machine may visibly reorder memory extent to which the machine may visibly reorder memory
accesses in order to optimize performance. Unfortunately, accesses to optimize performance. Unfortunately,
there are almost as many models as architectures. Moreover, there are almost as many models as architectures.
some architectures, for instance IA32 or Sparcv9 TSO, are Some architectures, for example IA32 or Sparcv9 TSO, are
relatively strongly ordered. In contrast, others, like relatively strongly ordered. In contrast, others, like
PowerPC or ARM, are very relaxed. In effect, atomics define a PowerPC or ARM, are very relaxed. In effect, atomics define a
very relaxed abstract memory model for &os;'s very relaxed abstract memory model for &os;'s
machine-independent code that can be efficiently realized on machine-independent code that can be efficiently realized on
any of these architectures.</p> any of these architectures.</p>
<p>However, most &os; development and testing still happens on <p>Most &os; development and testing still happens on
x86 machines, which, when combined with x86's strongly ordered x86 machines, which, when combined with x86's strongly ordered
memory model, leads to errors in the use of atomics, memory model, leads to errors in the use of atomics,
specifically, barriers. In other words, the code is not specifically, barriers. In other words, the code is not
@ -1365,7 +1368,7 @@
buffers at the micro-architecural level. So, to ensure buffers at the micro-architecural level. So, to ensure
sequentially consistent behavior on x86, a store/load barrier sequentially consistent behavior on x86, a store/load barrier
needs to be issued, which can be done with an MFENCE needs to be issued, which can be done with an MFENCE
instruction or by any locked RMW operation. The latter instruction or by any locked read-modify-write operation. The latter
approach is recommended by the optimization guides from Intel approach is recommended by the optimization guides from Intel
and AMD. It was noted that careful selection of the scratch and AMD. It was noted that careful selection of the scratch
memory location, which is modified by the locked RWM memory location, which is modified by the locked RWM
@ -1619,7 +1622,7 @@
</links> </links>
<body> <body>
<p>As of the end of Q3 the ports tree holds a bit more than <p>As of the end of Q3 the ports tree holds just over
25,000 ports, and the PR count is above 2,000. The summer 25,000 ports, and the PR count is above 2,000. The summer
period saw less activity on the ports tree than during the period saw less activity on the ports tree than during the
previous quarter, with fewer than 7,000 commits performed by previous quarter, with fewer than 7,000 commits performed by
@ -3115,7 +3118,7 @@
<body> <body>
<p>The Allwinner A10 and A20 chips are ARM CPUs found in <p>The Allwinner A10 and A20 chips are ARM CPUs found in
increasingly common development boards and other devices, like increasingly common development boards and other devices, such as
the Cubieboard/Cubieboard 2 and the Banana Pi.</p> the Cubieboard/Cubieboard 2 and the Banana Pi.</p>
<p>With the end of a GSoC project by Pratik Singhal, our A10 and <p>With the end of a GSoC project by Pratik Singhal, our A10 and