The pNFS server will be in need of testing during development - or it will never progress to a near-production status. I - hope to have code available in &os;'s Subversion project - branch for testing in late spring 2016.
+The pNFS server will be in need of testing during + development or it will never progress to a near-production + status. I hope to have code available in &os;'s Subversion + project branch for testing in late spring 2016.
This project aims to enable the use of the Signal Processing Engine found in the NXP/Freescale e500v2 SoC. The SPE uses - opcodes overlapping with those of Altivec, so they are mutually - exclusive. Additionally, the e500v2 does not have a traditional - FPU, and instead uses the SPE for all floating point operations - (or emulation, as is currently done). Combined with the fact - that the SPE ABI is incompatible with the traditional ABI, a new - MACHINE_ARCH has been created to address these - incompatibilities.
+ opcodes overlapping with those of Altivec, so they are + mutually exclusive. Additionally, the e500v2 does not have a + traditional FPU, and instead uses the SPE for all floating + point operations (or emulation, as is currently done). + Combined with the fact that the SPE ABI is incompatible with + the traditional ABI, a new MACHINE_ARCH has been created to + address these incompatibilities.A project branch has been created for the work. A powerpcspe kernel boots on the RouterBoard RB800, and the base @@ -556,8 +556,8 @@
The driver supports all available Ethernet connections (1, - 10, 30 Gbps) and the system can saturate a 10 Gbps link (on Tx) - using 4 CPU cores.
+ 10, 30 Gbps) and the system can saturate a 10 Gbps link (on + Tx) using 4 CPU cores.