From 1adff3888d9b7496dc5cbf0d19c658ae006a6353 Mon Sep 17 00:00:00 2001
From: John Fieber <jfieber@FreeBSD.org>
Date: Fri, 25 Aug 1995 22:14:30 +0000
Subject: [PATCH] Added some notes on PCI chipsets and their quirks. Submitted
 by:	jhk@freebsd.org for rgrimes@freebsd.org

---
 handbook/authors.sgml |  3 ++-
 handbook/hw.sgml      | 61 ++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 59 insertions(+), 5 deletions(-)

diff --git a/handbook/authors.sgml b/handbook/authors.sgml
index 0e8468fc73..07210c90d2 100644
--- a/handbook/authors.sgml
+++ b/handbook/authors.sgml
@@ -1,4 +1,4 @@
-<!-- $Id: authors.sgml,v 1.5 1995-07-29 13:08:00 jfieber Exp $ -->
+<!-- $Id: authors.sgml,v 1.6 1995-08-25 22:14:28 jfieber Exp $ -->
 <!-- The FreeBSD Documentation Project -->
 
 <!-- 
@@ -23,4 +23,5 @@ entities when referencing people.
 <!ENTITY a.nik "Nik Clayton <tt>&lt;nik@blueberry.co.uk&gt;</tt>">
 <!ENTITY a.phk "Poul-Henning Kamp <tt>&lt;phk@FreeBSD.org&gt;</tt>">
 <!ENTITY a.paul "Paul Richards <tt>&lt;paul@FreeBSD.org&gt;</tt>">
+<!ENTITY a.rgrimes "Rodney Grimes <tt>&lt;rgrimes@FreeBSD.org&gt;</tt>">
 <!ENTITY a.wilko "Wilko Bulte <tt>&lt;wilko@yedi.iaf.nl&gt;</tt>">
diff --git a/handbook/hw.sgml b/handbook/hw.sgml
index 64bfcc5e25..48c2dbb81f 100644
--- a/handbook/hw.sgml
+++ b/handbook/hw.sgml
@@ -1,6 +1,10 @@
-<!-- $Id: hw.sgml,v 1.2 1995-06-20 16:29:54 jfieber Exp $ -->
+<!-- $Id: hw.sgml,v 1.3 1995-08-25 22:14:30 jfieber Exp $ -->
 <!-- The FreeBSD Documentation Project -->
 
+<!--
+<!DOCTYPE linuxdoc PUBLIC "-//FreeBSD//DTD linuxdoc//EN">
+-->
+
 <chapt><heading>PC Hardware compatibility<label id="hw"></heading>
 
   <p>Issues of hardware compatibility are among the most
@@ -28,13 +32,62 @@
     FreeBSD you are using and include as many details of your
     hardware as possible.
 
-<sect><heading>* Core/Processing<label id="hw:core"></heading>
+<sect><heading>Core/Processing<label id="hw:core"></heading>
 
-<sect1><heading>* Motherboards</heading>
+<sect1><heading>Motherboards, busses, and chipsets</heading>
   <sect2><heading>* ISA</heading>
   <sect2><heading>* EISA</heading>
   <sect2><heading>* VLB</heading>
-  <sect2><heading>* PCI</heading>
+  <sect2><heading>PCI</heading>
+
+	  <p><em>Contributed by &a.rgrimes;.<newline>25 April 1995.</em></p>
+
+	  <p>Of the Intel PCI chip sets the following is a list
+	    of brokenness from worst to best and a short
+	    description of brokenness.</p>
+
+	  <p><descrip>
+
+	      <tag>Mercury:</tag> Cache coherency problems,
+		especially if there are ISA bus masters behind
+		the ISA to PCI bridge chip.  Hardware flaw, only
+		known work around is to turn the cache
+		off.
+
+	      <tag>Saturn-I <em>(ie, 82424ZX at rev 0, 1 or
+		2)</em>:</tag> write back cache coherency
+		problems.  Hardware flaw, only known work around
+		is to set the external cache to write-through
+		mode.  Upgrade to Saturn-II.
+
+	      <tag>Saturn-II <em>(ie, 82424ZX at rev 3 or
+		4)</em>:</tag> Works fine, but many MB
+		manufactures leave out the external dirty bit
+		SRAM needed for write back operation.  Work
+		arounds are either run it in write through mode,
+		or get the dirty bit SRAM installed.  (I have
+		these for the ASUS PCI/I-486SP3G rev 1.6 and
+		later boards).
+
+	      <tag>Neptune:</tag> Can not run more than 2 bus
+		master devices.  Admitted Intel design flaw.
+		Workarounds include don't run more than 2 bus
+		masters, special hardware design to replace the
+		PCI bus arbiter (appears on Intel Altair board
+		and several other Intel server group MB's).  And
+		of course Intel's official answer, move to the
+		Triton chip set, we ``fixed it there''.
+
+	      <tag>Triton:</tag> No known cache coherency or bus
+		master problems, chip set does not implement
+		parity checking.  Workaround for parity issue.
+		Wait for Triton-II.
+
+	      <tag>Triton-II:</tag> Unknown, not yet shipping.
+
+	    </descrip>
+	  </p>
+
 <sect1><heading>* CPUs/FPUs</heading>
 <sect1><heading>* Memory</heading>
 <sect1><heading>* BIOS</heading>