diff --git a/en_US.ISO8859-1/books/arch-handbook/boot/chapter.sgml b/en_US.ISO8859-1/books/arch-handbook/boot/chapter.sgml
index 17813172db..0acab47ae0 100644
--- a/en_US.ISO8859-1/books/arch-handbook/boot/chapter.sgml
+++ b/en_US.ISO8859-1/books/arch-handbook/boot/chapter.sgml
@@ -136,8 +136,8 @@ Timecounter "i8254"  frequency 1193182 Hz</screen></para></entry>
       after a power on is well defined: it is a 32-bit value of
       0xfffffff0.  The instruction pointer register points to code to
       be executed by the processor.  One of the registers is the
-      <literal>cr1</literal> 32-bit control register, and its value
-      just after the reboot is 0.  One of the cr1's bits, the bit PE
+      <literal>cr0</literal> 32-bit control register, and its value
+      just after the reboot is 0.  One of the cr0's bits, the bit PE
       (Protected Enabled) indicates whether the processor is running
       in protected or real mode.  Since at boot time this bit is
       cleared, the processor boots in real mode.  Real mode means,