From 29eaa0176d50c077ca4903a880b5ecdea9d1acbe Mon Sep 17 00:00:00 2001 From: Giorgos Keramidas Date: Mon, 9 Jan 2012 13:43:07 +0000 Subject: [PATCH] The 'Protection Enabled' bit is part of CR0 not CR1 register. Submitted by: Petros Barbagiannis (petros.barbagiannis at gmail) --- en_US.ISO8859-1/books/arch-handbook/boot/chapter.sgml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/en_US.ISO8859-1/books/arch-handbook/boot/chapter.sgml b/en_US.ISO8859-1/books/arch-handbook/boot/chapter.sgml index 17813172db..0acab47ae0 100644 --- a/en_US.ISO8859-1/books/arch-handbook/boot/chapter.sgml +++ b/en_US.ISO8859-1/books/arch-handbook/boot/chapter.sgml @@ -136,8 +136,8 @@ Timecounter "i8254" frequency 1193182 Hz after a power on is well defined: it is a 32-bit value of 0xfffffff0. The instruction pointer register points to code to be executed by the processor. One of the registers is the - cr1 32-bit control register, and its value - just after the reboot is 0. One of the cr1's bits, the bit PE + cr0 32-bit control register, and its value + just after the reboot is 0. One of the cr0's bits, the bit PE (Protected Enabled) indicates whether the processor is running in protected or real mode. Since at boot time this bit is cleared, the processor boots in real mode. Real mode means,