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Add entry on the Alpine SoC from Michal Stanek

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Benjamin Kaduk 2016-10-24 01:08:55 +00:00
parent 82d0d32c32
commit 5744e65d61
Notes: svn2git 2020-12-08 03:00:23 +00:00 
svn path=/head/; revision=49556
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en_US.ISO8859-1/htdocs/news/status/report-2016-07-2016-09.xml
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@ -861,4 +861,77 @@
review.</task>
</help>
</project>
<project cat='arch'>
<title>&os; on Annapurna Labs Alpine</title>
<contact>
<person>
<name>
<given>Jan</given>
<common>Medala</common>
</name>
<email>jan@semihalf.com</email>
</person>
<person>
<name>
<given>Michal</given>
<common>Stanek</common>
</name>
<email>mst@semihalf.com</email>
</person>
<person>
<name>
<given>Wojciech</given>
<common>Macek</common>
</name>
<email>wma@semihalf.com</email>
</person>
</contact>
<body>
<p>Alpine is a family of Platform-on-Chip devices, including
multi-core 32-bit (first-gen Alpine) and 64-bit (Alpine V2) ARM
CPUs, developed by Annapurna Labs.</p>
<p>The primary focus areas of the Alpine platform are
high-performance networking, storage and embedded applications. The
network subsystem features 10-, 25-, and 50-Gbit Ethernet
controllers with support for virtualization, load-balancing,
hardware offload and other advanced features.</p>
<p>A basic patch set has already been committed to HEAD including:</p>
<ul>
<li>PCIe Root Complex support</li>
<li>Cache Coherency Unit driver</li>
<li>North Bridge Service driver</li>
<li>Updated Alpine HAL</li>
<li>Extended MSI support in GICv2 and GICv3 code</li>
</ul>
<p>Additional work, such as an MSI-X driver and full Ethernet
support, is currently undergoing community review on Phabricator.</p>
<p>The multi-user SMP system is stable and fully working, along with
the 1G and 10G Ethernet links.</p>
<p>The interrupt management code has been adjusted to work with the
new INTRNG framework on both ARM32 and ARM64.</p>
</body>
<sponsor>
Annapurna Labs &mdash; an Amazon company
</sponsor>
<sponsor>
Semihalf
</sponsor>
</project>
</report>