Add 2017Q4 PowerNV entry from Wojciech Macek

This commit is contained in:
Benjamin Kaduk 2018-02-19 17:00:06 +00:00
parent 1a40e76e53
commit 83ef4cef30
Notes: svn2git 2020-12-08 03:00:23 +00:00
svn path=/head/; revision=51431

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@ -346,4 +346,109 @@
any ports mentioned here, please consider fixing them.</task>
</help>
</project>
<project cat='arch'>
<title>&os; on PowerNV (ppc64)</title>
<contact>
<person>
<name>
<given>Patryk</given>
<common>Duda</common>
</name>
<email>pdk@semihalf.com</email>
</person>
<person>
<name>
<given>Wojciech</given>
<common>Macek</common>
</name>
<email>wma@FreeBSD.org</email>
<email>wma@semihalf.com</email>
</person>
<person>
<name>
<given>Michal</given>
<common>Stanek</common>
</name>
<email>mst@semihalf.com</email>
</person>
<person>
<name>
<given>Nathan</given>
<common>Whitehorn</common>
</name>
<email>nw@FreeBSD.org</email>
</person>
</contact>
<links>
<url href="https://github.com/Semihalf/powernv">Semihalf PowerNV Official Repository</url>
<url href="https://github.com/open-power/skiboot">Skiboot Repository with the Latest OPAL Firmware</url>
</links>
<body>
<p> Semihalf is happy to announce that &os; is running on an IBM
Power8 processor. This project is a continuation of work done
by Nathan Whitehorn, who provided a basic support for a
PowerNV emulator.</p>
<p>The IBM Power8 family of CPUs offers superior performance
compared to previous CPUs in the Power series. It provides
complete NUMA support with up to 128 execution threads in
two-socket system (2 sockets, 8 cores per socket, 8 threads
per core). All I/O communication is handled by an integrated
PCIe interface equipped with multiple IOMMU engines.</p>
<p>The support for Power8 system running &os; in a non-virtualized
environment contains:</p>
<ul>
<li>A generic driver for the OPAL hypervisor</li>
<li><tt>kboot</tt> loader modifications to allow for a
little-endian to load a big-endian kernel ELF image</li>
<li>An update to the ELF parser in <tt>skiboot</tt>, allowing
it to understand the &os; kernel file format</li>
<li>Basic support for the PowerNV architecture, including
modes of operation, memory-management unit (MMU), and
interrupt controller</li>
<li>SMP operation with up to 128 CPUs</li>
<li>PCI host bridge subsystem driver, including IOMMU mapping
for external busses</li>
<li>PCIe host controller driver</li>
<li>USB-3.0 XHCI driver</li>
<li>Reworked several drivers to be big-endian compatible</li>
<li>Chelsio cxgbe(4) 10/25G network adapter</li>
<li>NVMe SSD driver</li>
</ul>
<p>All work is available in the linked GitHub repository. The
process of getting this work into the official repository has
already started and eventually, all commits will be integrated
into &os;-12 CURRENT.</p>
</body>
<sponsor>IBM</sponsor>
<sponsor>The FreeBSD Foundation</sponsor>
<sponsor>QCM Technologies</sponsor>
<sponsor>Semihalf</sponsor>
<sponsor>Limelight Networks (Kevin Bowling)</sponsor>
</project>
</report>