From 9814ea27d02eeffe7e345c10a264a1dbf367cb9c Mon Sep 17 00:00:00 2001 From: Daniel Gerzo Date: Wed, 25 Jan 2012 13:50:42 +0000 Subject: [PATCH] - add SandyBridge status reports Submitted by: kib --- en/news/status/report-2011-10-2011-12.xml | 49 ++++++++++++++++++++++- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/en/news/status/report-2011-10-2011-12.xml b/en/news/status/report-2011-10-2011-12.xml index 1545b4e6fb..af681a6c9a 100644 --- a/en/news/status/report-2011-10-2011-12.xml +++ b/en/news/status/report-2011-10-2011-12.xml @@ -1,7 +1,7 @@ - + October-December @@ -19,7 +19,7 @@ Report//EN" "http://www.FreeBSD.org/XML/www/share/sgml/statusreport.dtd"> the beginning of January 2012.

Thanks to all the reporters for the excellent work! This report - contains 29 entries and we hope you enjoy reading it.

+ contains 30 entries and we hope you enjoy reading it.

Please note that the deadline for submissions covering the period between January and March 2012 is April 15th, 2012.

@@ -1762,4 +1762,49 @@ Report//EN" "http://www.FreeBSD.org/XML/www/share/sgml/statusreport.dtd"> Test more hardware? + + + Improving support for new features in Intel SandyBridge CPUs + + + + + Konstantin + Belousov + + kib@FreeBSD.org + + + + +

Support for new features in the Intel SandyBridge CPUs is + progressing.

+ +

The patch to query and allow extended FPU states was committed, + which enabled the YMM registers and AVX instruction set on the + capable processors. Todo items include get wider testing of the + change before planned merge to stable/9 in a month, and start + using XSAVEOPT instruction to optimize context switch times.

+ +

Patch to enable and use per-process TLB was developed. Latest + version is available at + http://people.freebsd.org/~kib/misc/pcid.2.patch. The facility, + referred in the documentation as PCID, allows to avoid TLB flush + on context switches by applying PID tag to each non-global TLB + entry. On SandyBridge, measurements did not prove any difference + between context switch latencies on patched and stock kernels.

+ +

Forthcoming IvyBridge CPUs promised to provide optimizations in + the form of INVPCID instructions that allow to optimize TLB + shootdown handlers. Patch above uses the instruction on the + capable CPU. Todo items are to get access to IvyBridge and do the + benchmarks.

+ +

Future work might provde SEP support, use hardware random + generator from IvyBridge for random(4), considering using faster + instructions to access fs% and gs% bases, and use improved AES-NI + instruction set for aesni(4).

+ +