A revised version, that fixes typos, clarifies some points that caused
EMAIL questions, corrects a serious error in the I/O port map, and adds information on the recently released 32-bit superset Intel 82374 DMA controller appearing in PCI (and EISA) systems. I recommend this updated section be included in the 2.2.x tree ASAP. As always, comments and corrections are welcome. Frank Durda IV uhclem%freebsd.org or (checked more frequently) uhclem.freebsd%nemesis.lonestar.org Change % to @, or your RFC-822-compliant mail transport will do it for you.
This commit is contained in:
Frank Durda IV
parent
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Notes:
svn2git
2020-12-08 03:00:23 +00:00
svn path=/head/; revision=2041
1 changed files with 205 additions and 104 deletions
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@ -1,4 +1,4 @@
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<!-- $Id: dma.sgml,v 1.8 1997-08-12 09:17:46 asami Exp $ -->
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<!-- $Id: dma.sgml,v 1.9 1997-10-09 22:51:31 uhclem Exp $ -->
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<!-- The FreeBSD Documentation Project -->
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<!--
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@ -11,8 +11,8 @@
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-->
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<sect><heading>DMA: What it Is and How it Works<label id="dma"></heading>
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<p><em>Copyright © 1995 &a.uhclem;, All Rights Reserved.<newline>
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10 December 1996.</em>
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<p><em>Copyright © 1995,1997 &a.uhclem;, All Rights Reserved.<newline>
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10 December 1996. Last Update 8 October 1997.</em>
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<!-- Version 1(3) -->
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@ -63,26 +63,27 @@
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CPU.</quote>
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In the PC architecture, each DMA channel is normally
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activated only when the hardware that uses that DMA
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activated only when the hardware that uses a given DMA channel
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requests a transfer by asserting the DRQ line for that
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channel.
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<sect1><heading>A Sample DMA transfer</heading>
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<p>Here is an example of the steps that occur to cause a
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DMA transfer. In this example, the floppy disk
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<p>Here is an example of the steps that occur to cause and perform
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a DMA transfer. In this example, the floppy disk
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controller (FDC) has just read a byte from a diskette and
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wants the DMA to place it in memory at location
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0x00123456. The process begins by the FDC asserting the
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DRQ2 signal to alert the DMA controller.
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DRQ2 signal (the DRQ line for DMA channel 2) to alert the DMA
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controller.
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The DMA controller will note that the DRQ2 signal is asserted.
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The DMA controller will then make sure that DMA channel 2
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has been programmed and is enabled. The DMA controller
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has been programmed and is unmasked (enabled). The DMA controller
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also makes sure that none of the other DMA channels are active
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or have a higher priority. Once these checks are
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complete, the DMA asks the CPU to release the bus so that
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or want to be active and have a higher priority. Once these checks
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are complete, the DMA asks the CPU to release the bus so that
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the DMA may use the bus. The DMA requests the bus by
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asserting the HRQ signal which goes to the CPU.
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@ -124,8 +125,8 @@
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has been transferred.
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Since the DMA cycle only transfers a single byte at a
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time, the FDC now drops the DRQ2 signal, so that the DMA
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knows it is no longer needed. The DMA will de-assert the
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time, the FDC now drops the DRQ2 signal, so the DMA knows that
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it is no longer needed. The DMA will de-assert the
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-DACK2 signal, so that the FDC knows it must stop placing
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data on the bus.
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@ -144,28 +145,30 @@
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For a typical floppy disk sector, the above process is
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repeated 512 times, once for each byte. Each time a byte
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is transferred, the address register in the DMA is
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incremented and the counter that shows how many bytes are
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to be transferred is decremented.
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incremented and the counter in the DMA that shows how many
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bytes are to be transferred is decremented.
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When the counter reaches zero, the DMA asserts the EOP
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signal, which indicates that the counter has reached zero
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and no more data will be transferred until the DMA
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controller is reprogrammed by the CPU. This event is
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also called the Terminal Count (TC). There is only one
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EOP signal, because only one DMA channel can be active at
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any instant.
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EOP signal, and since only DMA channel can be active at
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any instant, the DMA channel that is currently active must
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be the DMA channel that just completed its task.
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If a peripheral wants to generate an interrupt when the
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transfer of a buffer is complete, it can test for its
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-DACK signal and the EOP signal both being asserted at
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-DACKn signal and the EOP signal both being asserted at
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the same time. When that happens, it means the DMA will not
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transfer any more information for that peripheral without
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intervention by the CPU. The peripheral can then assert
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one of the interrupt signals to get the processors'
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attention. The DMA chip itself is not capable of
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generating an interrupt. The peripheral and its
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attention. In the PC architecture, the DMA chip itself is not
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capable of generating an interrupt. The peripheral and its
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associated hardware is responsible for generating any
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interrupt that occurs.
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interrupt that occurs. Subsequently, it is possible to have
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a peripheral that uses DMA but does not use interrupts.
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It is important to understand that although the CPU
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always releases the bus to the DMA when the DMA makes the
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@ -192,12 +195,12 @@
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supported more than 64K of memory, something had to be
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done to allow the DMA to read or write memory locations
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above the 64K mark. What IBM did to solve this problem
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was to add a latch for each DMA channel that holds the
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upper bits of the address to be read to or written from.
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was to add an external data latch for each DMA channel that
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holds the upper bits of the address to be read to or written from.
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Whenever a DMA channel is active, the contents of that
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latch are written to the address bus and kept there until
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the DMA operation for the channel ends. These latches
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are called ``Page Registers''.
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the DMA operation for the channel ends. IBM called these latches
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``Page Registers''.
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So for our example above, the DMA would put the 0x3456
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part of the address on the bus, and the Page Register for
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@ -207,26 +210,27 @@
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Because the Page Register latch is independent of the DMA
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chip, the area of memory to be read or written must not
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span a 64K physical boundary. If the DMA accesses memory
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location 0xffff, after the transfer the DMA will then increment
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the address register and the DMA will access the next byte at
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location 0x0000, not 0x10000. The results of letting this
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happen are probably not intended.
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span a 64K physical boundary. For example, if the DMA accesses
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memory location 0xffff, after that transfer the DMA will then
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increment the address register and the DMA will access the next
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byte at location 0x0000, not 0x10000. The results of letting
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this happen are probably not intended.
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<quote><em>Note:</em> ``Physical'' 64K boundaries should
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not be confused with 8086-mode 64K ``Segments'', which
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are created by adding a segment register with an offset
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register. Page Registers have no address overlap.</quote>
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are created by mathematically adding a segment register with an
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offset register. Page Registers have no address overlap and
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are mathematically OR-ed together.</quote>
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To further complicate matters, the external DMA address
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latches on the PC/AT hold only eight bits, so that gives
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us 8+16=24 bits, which means that the DMA can only point
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at memory locations between 0 and 16Meg. For newer
|
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computers that allow more than 16Meg of memory, the
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computers that allow more than 16Meg of memory, the standard
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||||
PC-compatible DMA cannot access memory locations above 16Meg.
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To get around this restriction, operating systems will
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reserve a buffer in an area below 16Meg that also does not
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reserve a RAM buffer in an area below 16Meg that also does not
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span a physical 64K boundary. Then the DMA will be
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programmed to transfer data from the peripheral and into that
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buffer. Once the DMA has moved the data into this buffer,
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@ -241,6 +245,11 @@
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``Bounce Buffers''. In the MS-DOS world, they are
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sometimes called ``Smart Buffers''.
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<quote><em>Note:</em> A new implementation of the 8237, called the
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82374, allows 16 bits of page register to be specified, allows
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access to the entire 32 bit address space, without the use of
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bounce buffers.</quote>
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<sect1><heading>DMA Operational Modes and Settings</heading>
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@ -256,8 +265,8 @@
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immediately. The peripheral will request the DMA
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each time it is ready for another transfer.
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The floppy disk controller only has a one-byte
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buffer, so it uses this mode.
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The standard PC-compatible floppy disk controller (NEC 765)
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only has a one-byte buffer, so it uses this mode.
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<tag>Block/Demand</tag> Once the DMA acquires the
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@ -272,8 +281,8 @@
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Block transfer is started, it runs until the transfer
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count reaches zero. DRQ only needs to be asserted
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until -DACK is asserted. Demand Mode will transfer
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one more bytes until DRQ is de-asserted and the DMA
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pauses the transfer and releases the bus back to the CPU.
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one more bytes until DRQ is de-asserted, at which point the DMA
|
||||
suspends the transfer and releases the bus back to the CPU.
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When DRQ is asserted later, the transfer resumes where
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||||
it was suspended.
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@ -288,41 +297,42 @@
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to request the bus, but then the attached peripheral
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device is responsible for placing the addressing
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information on the bus instead of the DMA. This is also
|
||||
known as ``Bus Mastering''.
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||||
used to implement a technique known as ``Bus Mastering''.
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When a DMA channel in Cascade Mode receives control
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of the bus, the DMA does not place addresses and I/O
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||||
control signals on the bus like the DMA normally does
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||||
when it is active. Instead, the DMA only asserts the
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||||
-DACK signal for this channel.
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-DACK signal for the active DMA channel.
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||||
|
||||
At this point it is up to the device connected to that DMA
|
||||
channel to provide address and bus control signals.
|
||||
At this point it is up to the peripheral connected to that
|
||||
DMA channel to provide address and bus control signals.
|
||||
The peripheral has complete control over the system
|
||||
bus, and can do reads and/or writes to any address
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||||
below 16Meg. When the peripheral is finished with
|
||||
the bus, it de-asserts the DRQ line, and the DMA
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||||
controller can return control to the CPU or to some
|
||||
controller can then return control to the CPU or to some
|
||||
other DMA channel.
|
||||
|
||||
Cascade Mode can be used to chain multiple DMA
|
||||
controllers together, and this is exactly what DMA
|
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Channel 4 is used for in the PC. When a peripheral
|
||||
requests the bus on DMA channels 0, 1, 2 or 3, the
|
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slave DMA controller asserts HLDREQ, but this wire is
|
||||
actually connected to DRQ4 on the primary DMA
|
||||
controller. The primary DMA controller then requests
|
||||
the bus from the CPU using HLDREQ. Once the bus is
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||||
granted, -DACK4 is asserted, and that wire is
|
||||
actually connected to the HLDA signal on the slave
|
||||
DMA controller. The slave DMA controller then
|
||||
transfers data for the DMA channel that requested it,
|
||||
or the slave DMA may grant the bus to a peripheral
|
||||
that wants to perform its own bus-mastering, such as
|
||||
a SCSI controller.
|
||||
Cascade Mode can be used to chain multiple DMA controllers
|
||||
together, and this is exactly what DMA Channel 4 is used
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for in the PC architecture. When a peripheral requests
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the bus on DMA channels 0, 1, 2 or 3, the slave DMA
|
||||
controller asserts HLDREQ, but this wire is actually connected
|
||||
to DRQ4 on the primary DMA controller instead of to the CPU.
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The primary DMA controller, thinking it has work to do on
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Channel 4, requests the bus from the CPU using HLDREQ signal.
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Once the CPU grants the bus to the primary DMA controller,
|
||||
-DACK4 is asserted, and that wire is actually connected to
|
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the HLDA signal on the slave DMA controller. The slave DMA
|
||||
controller then transfers data for the DMA channel that
|
||||
requested it (0, 1, 2 or 3), or the slave DMA may grant the bus
|
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to a peripheral that wants to perform its own bus-mastering,
|
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such as a SCSI controller.
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|
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Because of this wiring arrangement, only DMA channels
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0, 1, 2, 3, 5, 6 and 7 are usable on PC/AT systems.
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0, 1, 2, 3, 5, 6 and 7 are usable with peripherals on PC/AT
|
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systems.
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|
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<quote><em>Note:</em> DMA channel 0 was reserved for
|
||||
refresh operations in early IBM PC computers, but
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|
|
@ -386,9 +396,9 @@
|
|||
|
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<p>The DMA channel that is to be programmed should always
|
||||
be ``masked'' before loading any settings. This is because
|
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the hardware might unexpectedly assert DRQ, and the DMA might
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respond, even though not all of the parameters have been
|
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loaded or updated.
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the hardware might unexpectedly assert the DRQ for that channel,
|
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and the DMA might respond, even though not all of the parameters
|
||||
have been loaded or updated.
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||||
Once masked, the host must specify the direction of the
|
||||
transfer (memory-to-I/O or I/O-to-memory), what mode of
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||||
|
|
@ -408,13 +418,14 @@
|
|||
|
||||
Once all the settings are ready, the DMA channel can be
|
||||
un-masked. That DMA channel is now considered to be
|
||||
``armed'', and will respond when DRQ is asserted.
|
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``armed'', and will respond when the DRQ line for that channel
|
||||
is asserted.
|
||||
|
||||
Refer to a hardware data book for precise programming
|
||||
details for the 8237. You will also need to refer to the
|
||||
I/O port map for the PC system, which describes where
|
||||
the DMA and Page Register ports are located. A complete
|
||||
table is located below.
|
||||
port map table is located below.
|
||||
|
||||
|
||||
<sect1><heading>DMA Port Map</heading>
|
||||
|
|
@ -431,44 +442,44 @@
|
|||
<verb>
|
||||
0x00 write Channel 0 starting address
|
||||
0x00 read Channel 0 current address
|
||||
0x02 write Channel 0 starting word count
|
||||
0x02 read Channel 0 remaining word count
|
||||
0x01 write Channel 0 starting word count
|
||||
0x01 read Channel 0 remaining word count
|
||||
|
||||
0x04 write Channel 1 starting address
|
||||
0x04 read Channel 1 current address
|
||||
0x06 write Channel 1 starting word count
|
||||
0x06 read Channel 1 remaining word count
|
||||
0x02 write Channel 1 starting address
|
||||
0x02 read Channel 1 current address
|
||||
0x03 write Channel 1 starting word count
|
||||
0x03 read Channel 1 remaining word count
|
||||
|
||||
0x08 write Channel 2 starting address
|
||||
0x08 read Channel 2 current address
|
||||
0x0a write Channel 2 starting word count
|
||||
0x0a read Channel 2 remaining word count
|
||||
0x04 write Channel 2 starting address
|
||||
0x04 read Channel 2 current address
|
||||
0x05 write Channel 2 starting word count
|
||||
0x05 read Channel 2 remaining word count
|
||||
|
||||
0x0c write Channel 3 starting address
|
||||
0x0c read Channel 3 current address
|
||||
0x0e write Channel 3 starting word count
|
||||
0x0e read Channel 3 remaining word count
|
||||
0x06 write Channel 3 starting address
|
||||
0x06 read Channel 3 current address
|
||||
0x07 write Channel 3 starting word count
|
||||
0x07 read Channel 3 remaining word count
|
||||
</verb>
|
||||
|
||||
DMA Command Registers
|
||||
|
||||
<verb>
|
||||
0x10 write Command Register
|
||||
0x10 read Status Register
|
||||
0x12 write Request Register
|
||||
0x12 read -
|
||||
0x14 write Single Mask Register Bit
|
||||
0x14 read -
|
||||
0x16 write Mode Register
|
||||
0x16 read -
|
||||
0x18 write Clear LSB/MSB Flip-Flop
|
||||
0x18 read -
|
||||
0x1a write Master Clear/Reset
|
||||
0x1a read Temporary Register
|
||||
0x1c write Clear Mask Register
|
||||
0x1c read -
|
||||
0x1e write Write All Mask Register Bits
|
||||
0x1e read -
|
||||
0x08 write Command Register
|
||||
0x08 read Status Register
|
||||
0x09 write Request Register
|
||||
0x09 read -
|
||||
0x0a write Single Mask Register Bit
|
||||
0x0a read -
|
||||
0x0b write Mode Register
|
||||
0x0b read -
|
||||
0x0c write Clear LSB/MSB Flip-Flop
|
||||
0x0c read -
|
||||
0x0d write Master Clear/Reset
|
||||
0x0d read Temporary Register (not available on newer versions)
|
||||
0x0e write Clear Mask Register
|
||||
0x0e read -
|
||||
0x0f write Write All Mask Register Bits
|
||||
0x0f read Read All Mask Register Bits (only in Intel 82374)
|
||||
</verb>
|
||||
|
||||
<sect2><heading>0xc0 - 0xdf DMA Controller #2 (Channels 4, 5, 6 and 7)</heading>
|
||||
|
|
@ -511,25 +522,115 @@ DMA Command Registers
|
|||
0xd8 write Clear LSB/MSB Flip-Flop
|
||||
0xd8 read -
|
||||
0xda write Master Clear/Reset
|
||||
0xda read Temporary Register
|
||||
0xda read Temporary Register (not present in Intel 82374)
|
||||
0xdc write Clear Mask Register
|
||||
0xdc read -
|
||||
0xde write Write All Mask Register Bits
|
||||
0xde read -
|
||||
0xdf read Read All Mask Register Bits (only in Intel 82374)
|
||||
</verb>
|
||||
|
||||
<sect2><heading>0x80 - 0x9f DMA Page Registers</heading>
|
||||
|
||||
<p><verb>
|
||||
0x87 r/w DMA Channel 0
|
||||
0x83 r/w DMA Channel 1
|
||||
0x81 r/w DMA Channel 2
|
||||
0x82 r/w DMA Channel 3
|
||||
0x87 r/w Channel 0 Low byte (23-16) page Register
|
||||
0x83 r/w Channel 1 Low byte (23-16) page Register
|
||||
0x81 r/w Channel 2 Low byte (23-16) page Register
|
||||
0x82 r/w Channel 3 Low byte (23-16) page Register
|
||||
|
||||
0x8b r/w DMA Channel 5
|
||||
0x89 r/w DMA Channel 6
|
||||
0x8a r/w DMA Channel 7
|
||||
|
||||
0x8f Refresh
|
||||
0x8b r/w Channel 5 Low byte (23-16) page Register
|
||||
0x89 r/w Channel 6 Low byte (23-16) page Register
|
||||
0x8a r/w Channel 7 Low byte (23-16) page Register
|
||||
0x8f r/w Low byte page Refresh
|
||||
</verb>
|
||||
|
||||
<sect2><heading>0x400 - 0x4ff 82374 Enhanced DMA Registers</heading>
|
||||
|
||||
<p>
|
||||
The Intel 82374 EISA System Component (ESC) was introduced in early 1996
|
||||
and includes a DMA controller that provides a superset of 8237 functionality
|
||||
as well as other PC-compatible core peripheral components in a single
|
||||
package. This chip is targeted at both EISA and PCI platforms, and provides
|
||||
modern DMA features like scatter-gather, ring buffers as well as direct
|
||||
access by the system DMA to all 32 bits of address space.
|
||||
|
||||
<p>
|
||||
If these features are used, code should also be included to provide similar
|
||||
functionality in the previous 16 years worth of PC-compatible computers.
|
||||
For compatibility reasons, some of the 82374 registers must be programmed
|
||||
<em>after</em> programming the traditional 8237 registers for each
|
||||
transfer. Writing to a traditional 8237 register forces the contents
|
||||
of some of the 82374 enhanced registers to zero to provide backward
|
||||
software compatibility.
|
||||
|
||||
|
||||
<p><verb>
|
||||
0x401 r/w Channel 0 High byte (bits 23-16) word count
|
||||
0x403 r/w Channel 1 High byte (bits 23-16) word count
|
||||
0x405 r/w Channel 2 High byte (bits 23-16) word count
|
||||
0x407 r/w Channel 3 High byte (bits 23-16) word count
|
||||
0x4c6 r/w Channel 5 High byte (bits 23-16) word count
|
||||
0x4ca r/w Channel 6 High byte (bits 23-16) word count
|
||||
0x4ce r/w Channel 7 High byte (bits 23-16) word count
|
||||
|
||||
0x487 r/w Channel 0 High byte (bits 31-24) page Register
|
||||
0x483 r/w Channel 1 High byte (bits 31-24) page Register
|
||||
0x481 r/w Channel 2 High byte (bits 31-24) page Register
|
||||
0x482 r/w Channel 3 High byte (bits 31-24) page Register
|
||||
0x48b r/w Channel 5 High byte (bits 31-24) page Register
|
||||
0x489 r/w Channel 6 High byte (bits 31-24) page Register
|
||||
0x48a r/w Channel 6 High byte (bits 31-24) page Register
|
||||
0x48f r/w High byte page Refresh
|
||||
|
||||
0x4e0 r/w Channel 0 Stop Register (bits 7-2)
|
||||
0x4e1 r/w Channel 0 Stop Register (bits 15-8)
|
||||
0x4e2 r/w Channel 0 Stop Register (bits 23-16)
|
||||
0x4e4 r/w Channel 1 Stop Register (bits 7-2)
|
||||
0x4e5 r/w Channel 1 Stop Register (bits 15-8)
|
||||
0x4e6 r/w Channel 1 Stop Register (bits 23-16)
|
||||
0x4e8 r/w Channel 2 Stop Register (bits 7-2)
|
||||
0x4e9 r/w Channel 2 Stop Register (bits 15-8)
|
||||
0x4ea r/w Channel 2 Stop Register (bits 23-16)
|
||||
0x4ec r/w Channel 3 Stop Register (bits 7-2)
|
||||
0x4ed r/w Channel 3 Stop Register (bits 15-8)
|
||||
0x4ee r/w Channel 3 Stop Register (bits 23-16)
|
||||
0x4f4 r/w Channel 5 Stop Register (bits 7-2)
|
||||
0x4f5 r/w Channel 5 Stop Register (bits 15-8)
|
||||
0x4f6 r/w Channel 5 Stop Register (bits 23-16)
|
||||
0x4f8 r/w Channel 6 Stop Register (bits 7-2)
|
||||
0x4f9 r/w Channel 6 Stop Register (bits 15-8)
|
||||
0x4fa r/w Channel 6 Stop Register (bits 23-16)
|
||||
0x4fc r/w Channel 7 Stop Register (bits 7-2)
|
||||
0x4fd r/w Channel 7 Stop Register (bits 15-8)
|
||||
0x4fe r/w Channel 7 Stop Register (bits 23-16)
|
||||
|
||||
0x40a write Channels 0-3 Chaining Mode Register
|
||||
0x40a read Channel Interrupt Status Register
|
||||
0x4d4 write Channels 4-7 Chaining Mode Register
|
||||
0x4d4 read Chaining Mode Status
|
||||
0x40c read Chain Buffer Expiration Control Register
|
||||
|
||||
0x410 write Channel 0 Scatter-Gather Command Register
|
||||
0x411 write Channel 1 Scatter-Gather Command Register
|
||||
0x412 write Channel 2 Scatter-Gather Command Register
|
||||
0x413 write Channel 3 Scatter-Gather Command Register
|
||||
0x415 write Channel 5 Scatter-Gather Command Register
|
||||
0x416 write Channel 6 Scatter-Gather Command Register
|
||||
0x417 write Channel 7 Scatter-Gather Command Register
|
||||
|
||||
0x418 read Channel 0 Scatter-Gather Status Register
|
||||
0x419 read Channel 1 Scatter-Gather Status Register
|
||||
0x41a read Channel 2 Scatter-Gather Status Register
|
||||
0x41b read Channel 3 Scatter-Gather Status Register
|
||||
0x41d read Channel 5 Scatter-Gather Status Register
|
||||
0x41e read Channel 5 Scatter-Gather Status Register
|
||||
0x41f read Channel 7 Scatter-Gather Status Register
|
||||
|
||||
0x420-0x423 r/w Channel 0 Scatter-Gather Descripter Table Pointer Register
|
||||
0x424-0x427 r/w Channel 1 Scatter-Gather Descripter Table Pointer Register
|
||||
0x428-0x42b r/w Channel 2 Scatter-Gather Descripter Table Pointer Register
|
||||
0x42c-0x42f r/w Channel 3 Scatter-Gather Descripter Table Pointer Register
|
||||
0x434-0x437 r/w Channel 5 Scatter-Gather Descripter Table Pointer Register
|
||||
0x438-0x43b r/w Channel 6 Scatter-Gather Descripter Table Pointer Register
|
||||
0x43c-0x43f r/w Channel 7 Scatter-Gather Descripter Table Pointer Register
|
||||
</verb>
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue