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Add RISC-V entry from br

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Benjamin Kaduk 2016-01-18 07:02:29 +00:00
parent 67aee3b18f
commit ded1d801a7
Notes: svn2git 2020-12-08 03:00:23 +00:00 
svn path=/head/; revision=48053
1 changed files with 68 additions and 0 deletions
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en_US.ISO8859-1/htdocs/news/status/report-2015-10-2015-12.xml
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@ -3563,4 +3563,72 @@
</task> </task>
</help> </help>
</project> </project>
<project cat='arch'>
<title>&os;/RISC-V</title>
<contact>
<person>
<name>
<given>Ruslan</given>
<common>Bukin</common>
</name>
<email>br@bsdpad.com</email>
</person>
<person>
<name>
<given>Ed</given>
<common>Maste</common>
</name>
<email>emaste@FreeBSD.org</email>
</person>
<person>
<name>
<given>Arun</given>
<common>Thomas</common>
</name>
<email>arun.thomas@baesystems.com</email>
</person>
</contact>
<links>
<url href="https://wiki.FreeBSD.org/riscv">Project Wiki</url>
</links>
<body>
<p>We have begun work on support for the RISC-V
architecture.</p>
<p>RISC-V is a new ISA designed to support computer
architecture research and education that is now set to become a
standard open architecture for industry implementations.</p>
<p>A minimal set of changes needed to compile the kernel
toolchain has been committed, along with machine headers and
run-time linker (rtld-elf) support.</p>
<p>All development has been happening in a separate branch,
with a goal of moving development to head in a few weeks.</p>
<p>At present, &os;/RISC-V boots to multiuser in the Spike
simulator.</p>
</body>
<sponsor>
DARPA, AFRL
</sponsor>
<sponsor>
HEIF5
</sponsor>
<help>
<task>
<p>We plan to commit the rest of userspace (i.e,. libc),
kernel support, etc., in a few weeks.</p>
</task>
</help>
</project>
</report> </report>