Add report on support for new x86 platform features
DMAR, VT-d featuers, x2APIC, EOI suppression, and more. Approved by: hrs (mentor, implicit)
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Benjamin Kaduk
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2020-12-08 03:00:23 +00:00
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@ -1713,4 +1713,93 @@ WITHOUT_FORTH=y</pre>
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</task>
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</help>
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</project>
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<project cat='kern'>
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<title>Modern x86 platform support and VT-d</title>
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<contact>
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<person>
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<name>
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<given>Konstantin</given>
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<common>Belousov</common>
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</name>
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<email>kib@FreeBSD.org</email>
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</person>
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</contact>
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<body>
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<p>Modern x86 platforms include a number of architectural
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enhancements. Work is ongoing to support these features in
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&os;.</p>
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<p>Starting with SandyBridge CPUs, Intel introduced an
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enchanced local interrupt controller (APIC) mode, called x2APIC.
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Instead of using a mapped page, registers are now accessed using
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special Model-Specific Registers (MSR) read and write
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instructions. This is intended to support virtualization. The
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access overhead is also reduced by not requiring serialization,
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and by simplification of Inter-Process Interrups (IPI)
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generation. The main commit introducing the feature was
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r278473, with fixes following on.</p>
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<p>End Of Interrupt (EOI) suppression is a mode of EOI
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delivery to Input/Output Interrupt Controllers (IO-APICs) where
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the EOI message for a level-triggered interrupt is not broadcast
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by an EOI write to the local APIC, but instead an explicit EOI
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command is sent to the source IO-APIC. The optimization reduces
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the number of APIC messages that must be broadcast. It should
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be used on all modern Intel systems. Support for EOI
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suppression was committed in r279319.</p>
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<p>VT-d Interrupt Remapping (IR) is provided by hardware
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with the VT-d feature. It translates interrupt messages on the
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way from the root complex to the north bridge and allows control
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of interrupt delivery without reprogramming MSI/MSI-X registers
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or IO-APICs. The original intent was to allow hypervisors to
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safely delegate interrupt programming for devices owned by
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guests to the guest OS. But IR is also needed to avoid some
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limitations in IO-APICs and to make interrupt rebalancing atomic
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and transparent. Support has been committed as r280260.</p>
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<p>Both x2APIC mode and IR are required to send IPIs and
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device interrupts to processors with LAPIC ID greater then 254.
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It is believed that the only missing platform code to handle big
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machines is parsing the "Processor Local x2APIC Structure" and
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"Local x2APIC NMI Structure" from the ACPI Multiple APIC
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Description Table (MADT), which report LAPIC IDs > 255, and
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handling boot on such systems with the x2APIC mode enabled by
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firmware. The work to complete that is expected to be
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relatively trivial, and can be done with access to a real
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high-core-count machine. But an audit of the common
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machine-independent code must be finished to ensure that large
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CPU IDs are handled correctly, before such support can
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safely be enabled..</p>
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<p>Additional work remains in progress: split domains and
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contexts for DMA Remapper Unit (DMAR) driver. Right now, the
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DMAR driver is only used to implement busdma(9), which is done
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by assigning a dedicated domain to each translation context.
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Some devices could issue PCIe Transaction Laeyer Packets (TLPs)
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with several originators IDs, e.g., PCIe/PCI bridges, or
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phantom functions of PCIe devices, or such TLPs could occur just
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due to hardware bugs. To handle them, a single domain (which
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shares the translation page tables) must handle several
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contexts.</p>
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<p>Splitting domains and contexts is also required for the
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DMAR driver to start handling PCI pass-through in bhyve, instead
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of the less complete implementation which is currently provided
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by bhyve itself. All PCIe devices passed to the guest must
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share a domain. The splitting patch is written and is being
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tested, and external interfaces to manage domains are being
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formed.</p>
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<p>Stability work for the VT-d code is ongoing. In
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particular, nvme(4) and ixgbe(4)'s use of busdma interfaces was
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debugged and improved, and tested on a very large-memory
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machine.</p>
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</body>
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<sponsor>The &os; Foundation</sponsor>
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</project>
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</report>
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