636 lines
27 KiB
Text
636 lines
27 KiB
Text
<!-- $Id: dma.sgml,v 1.10 1997-10-19 13:32:09 jraynard Exp $ -->
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<!-- The FreeBSD Documentation Project -->
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]>
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<sect><heading>DMA: What it Is and How it Works<label id="dma"></heading>
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<p><em>Copyright © 1995,1997 &a.uhclem;, All Rights Reserved.<newline>
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10 December 1996. Last Update 8 October 1997.</em>
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<!-- Version 1(3) -->
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Direct Memory Access (DMA) is a method of allowing data to
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be moved from one location to another in a computer without
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intervention from the central processor (CPU).
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The way that the DMA function is implemented varies between
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computer architectures, so this discussion will limit
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itself to the implementation and workings of the DMA
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subsystem on the IBM Personal Computer (PC), the IBM PC/AT
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and all of its successors and clones.
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The PC DMA subsystem is based on the Intel 8237 DMA
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controller. The 8237 contains four DMA channels that can
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be programmed independently and any one of the channels may be
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active at any moment. These channels are numbered 0, 1, 2
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and 3. Starting with the PC/AT, IBM added a second 8237
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chip, and numbered those channels 4, 5, 6 and 7.
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The original DMA controller (0, 1, 2 and 3) moves one byte
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in each transfer. The second DMA controller (4, 5, 6, and
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7) moves 16-bits from two adjacent memory locations in each
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transfer, with the first byte always coming from an even-numbered
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address. The two controllers are identical components and the
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difference in transfer size is caused by the way the second
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controller is wired into the system.
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The 8237 has two electrical signals for each channel, named
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DRQ and -DACK. There are additional signals with the
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names HRQ (Hold Request), HLDA (Hold Acknowledge), -EOP
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(End of Process), and the bus control signals -MEMR (Memory
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Read), -MEMW (Memory Write), -IOR (I/O Read), and -IOW (I/O
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Write).
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The 8237 DMA is known as a ``fly-by'' DMA controller. This
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means that the data being moved from one location to
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another does not pass through the DMA chip and is not
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stored in the DMA chip. Subsequently, the DMA can only
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transfer data between an I/O port and a memory address, but
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not between two I/O ports or two memory locations.
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<quote><em>Note:</em> The 8237 does allow two channels to
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be connected together to allow memory-to-memory DMA
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operations in a non-``fly-by'' mode, but nobody in the PC
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industry uses this scarce resource this way since it is
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faster to move data between memory locations using the
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CPU.</quote>
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In the PC architecture, each DMA channel is normally
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activated only when the hardware that uses a given DMA channel
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requests a transfer by asserting the DRQ line for that
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channel.
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<sect1><heading>A Sample DMA transfer</heading>
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<p>Here is an example of the steps that occur to cause and perform
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a DMA transfer. In this example, the floppy disk
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controller (FDC) has just read a byte from a diskette and
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wants the DMA to place it in memory at location
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0x00123456. The process begins by the FDC asserting the
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DRQ2 signal (the DRQ line for DMA channel 2) to alert the DMA
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controller.
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The DMA controller will note that the DRQ2 signal is asserted.
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The DMA controller will then make sure that DMA channel 2
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has been programmed and is unmasked (enabled). The DMA controller
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also makes sure that none of the other DMA channels are active
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or want to be active and have a higher priority. Once these checks
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are complete, the DMA asks the CPU to release the bus so that
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the DMA may use the bus. The DMA requests the bus by
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asserting the HRQ signal which goes to the CPU.
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The CPU detects the HRQ signal, and will complete
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executing the current instruction. Once the processor
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has reached a state where it can release the bus, it
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will. Now all of the signals normally generated by the
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CPU (-MEMR, -MEMW, -IOR, -IOW and a few others) are
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placed in a tri-stated condition (neither high or low)
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and then the CPU asserts the HLDA signal which tells the
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DMA controller that it is now in charge of the bus.
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Depending on the processor, the CPU may be able to
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execute a few additional instructions now that it no
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longer has the bus, but the CPU will eventually have to
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wait when it reaches an instruction that must read
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something from memory that is not in the internal
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processor cache or pipeline.
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Now that the DMA ``is in charge'', the DMA activates its
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-MEMR, -MEMW, -IOR, -IOW output signals, and the address
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outputs from the DMA are set to 0x3456, which will be
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used to direct the byte that is about to transferred to a
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specific memory location.
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The DMA will then let the device that requested the DMA
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transfer know that the transfer is commencing. This is
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done by asserting the -DACK signal, or in the case of the
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floppy disk controller, -DACK2 is asserted.
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The floppy disk controller is now responsible for placing
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the byte to be transferred on the bus Data lines. Unless
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the floppy controller needs more time to get the data
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byte on the bus (and if the peripheral does need more time it
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alerts the DMA via the READY signal), the DMA will wait
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one DMA clock, and then de-assert the -MEMW and -IOR
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signals so that the memory will latch and store the byte
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that was on the bus, and the FDC will know that the byte
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has been transferred.
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Since the DMA cycle only transfers a single byte at a
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time, the FDC now drops the DRQ2 signal, so the DMA knows that
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it is no longer needed. The DMA will de-assert the
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-DACK2 signal, so that the FDC knows it must stop placing
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data on the bus.
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The DMA will now check to see if any of the other DMA
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channels have any work to do. If none of the channels
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have their DRQ lines asserted, the DMA controller has
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completed its work and will now tri-state the -MEMR,
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-MEMW, -IOR, -IOW and address signals.
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Finally, the DMA will de-assert the HRQ signal. The CPU
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sees this, and de-asserts the HOLDA signal. Now the CPU
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activates its -MEMR, -MEMW, -IOR, -IOW and address lines,
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and it resumes executing instructions and accessing main
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memory and the peripherals.
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For a typical floppy disk sector, the above process is
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repeated 512 times, once for each byte. Each time a byte
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is transferred, the address register in the DMA is
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incremented and the counter in the DMA that shows how many
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bytes are to be transferred is decremented.
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When the counter reaches zero, the DMA asserts the EOP
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signal, which indicates that the counter has reached zero
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and no more data will be transferred until the DMA
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controller is reprogrammed by the CPU. This event is
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also called the Terminal Count (TC). There is only one
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EOP signal, and since only DMA channel can be active at
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any instant, the DMA channel that is currently active must
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be the DMA channel that just completed its task.
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If a peripheral wants to generate an interrupt when the
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transfer of a buffer is complete, it can test for its
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-DACKn signal and the EOP signal both being asserted at
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the same time. When that happens, it means the DMA will not
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transfer any more information for that peripheral without
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intervention by the CPU. The peripheral can then assert
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one of the interrupt signals to get the processors'
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attention. In the PC architecture, the DMA chip itself is not
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capable of generating an interrupt. The peripheral and its
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associated hardware is responsible for generating any
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interrupt that occurs. Subsequently, it is possible to have
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a peripheral that uses DMA but does not use interrupts.
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It is important to understand that although the CPU
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always releases the bus to the DMA when the DMA makes the
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request, this action is invisible to both applications
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and the operating systems, except for slight changes in
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the amount of time the processor takes to execute
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instructions when the DMA is active. Subsequently, the
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processor must poll the peripheral, poll the registers in
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the DMA chip, or receive an interrupt from the peripheral
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to know for certain when a DMA transfer has completed.
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<sect1><heading>DMA Page Registers and 16Meg address space limitations</heading>
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<p>You may have noticed earlier that instead of the DMA
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setting the address lines to 0x00123456 as we said
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earlier, the DMA only set 0x3456. The reason for this
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takes a bit of explaining.
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When the original IBM PC was designed, IBM elected to use
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both DMA and interrupt controller chips that were
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designed for use with the 8085, an 8-bit processor with
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an address space of 16 bits (64K). Since the IBM PC
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supported more than 64K of memory, something had to be
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done to allow the DMA to read or write memory locations
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above the 64K mark. What IBM did to solve this problem
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was to add an external data latch for each DMA channel that
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holds the upper bits of the address to be read to or written from.
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Whenever a DMA channel is active, the contents of that
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latch are written to the address bus and kept there until
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the DMA operation for the channel ends. IBM called these latches
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``Page Registers''.
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So for our example above, the DMA would put the 0x3456
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part of the address on the bus, and the Page Register for
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DMA channel 2 would put 0x0012xxxx on the bus. Together,
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these two values form the complete address in memory that
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is to be accessed.
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Because the Page Register latch is independent of the DMA
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chip, the area of memory to be read or written must not
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span a 64K physical boundary. For example, if the DMA accesses
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memory location 0xffff, after that transfer the DMA will then
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increment the address register and the DMA will access the next
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byte at location 0x0000, not 0x10000. The results of letting
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this happen are probably not intended.
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<quote><em>Note:</em> ``Physical'' 64K boundaries should
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not be confused with 8086-mode 64K ``Segments'', which
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are created by mathematically adding a segment register with an
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offset register. Page Registers have no address overlap and
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are mathematically OR-ed together.</quote>
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To further complicate matters, the external DMA address
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latches on the PC/AT hold only eight bits, so that gives
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us 8+16=24 bits, which means that the DMA can only point
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at memory locations between 0 and 16Meg. For newer
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computers that allow more than 16Meg of memory, the standard
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PC-compatible DMA cannot access memory locations above 16Meg.
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To get around this restriction, operating systems will
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reserve a RAM buffer in an area below 16Meg that also does not
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span a physical 64K boundary. Then the DMA will be
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programmed to transfer data from the peripheral and into that
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buffer. Once the DMA has moved the data into this buffer,
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the operating system will then copy the data from the buffer
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to the address where the data is really supposed to be stored.
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When writing data from an address above 16Meg to a
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DMA-based peripheral, the data must be first copied from
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where it resides into a buffer located below 16Meg, and
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then the DMA can copy the data from the buffer to the
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hardware. In FreeBSD, these reserved buffers are called
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``Bounce Buffers''. In the MS-DOS world, they are
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sometimes called ``Smart Buffers''.
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<quote><em>Note:</em> A new implementation of the 8237, called the
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82374, allows 16 bits of page register to be specified, allows
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access to the entire 32 bit address space, without the use of
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bounce buffers.</quote>
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<sect1><heading>DMA Operational Modes and Settings</heading>
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<p>The 8237 DMA can be operated in several modes. The main
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ones are:
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<descrip>
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<tag/Single/ A single byte (or word) is transferred.
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The DMA must release and re-acquire the bus for each
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additional byte. This is commonly-used by devices
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that cannot transfer the entire block of data
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immediately. The peripheral will request the DMA
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each time it is ready for another transfer.
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The standard PC-compatible floppy disk controller (NEC 765)
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only has a one-byte buffer, so it uses this mode.
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<tag>Block/Demand</tag> Once the DMA acquires the
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system bus, an entire block of data is transferred,
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up to a maximum of 64K. If the peripheral needs
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additional time, it can assert the READY signal to
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suspend the transfer briefly. READY should not be
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used excessively, and for slow peripheral transfers,
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the Single Transfer Mode should be used instead.
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The difference between Block and Demand is that once a
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Block transfer is started, it runs until the transfer
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count reaches zero. DRQ only needs to be asserted
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until -DACK is asserted. Demand Mode will transfer
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one more bytes until DRQ is de-asserted, at which point the DMA
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suspends the transfer and releases the bus back to the CPU.
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When DRQ is asserted later, the transfer resumes where
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it was suspended.
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Older hard disk controllers used Demand Mode until
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CPU speeds increased to the point that it was more
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efficient to transfer the data using the CPU, particularly
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if the memory locations used in the transfer were above the
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16Meg mark.
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<tag>Cascade</tag> This mechanism allows a DMA channel
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to request the bus, but then the attached peripheral
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device is responsible for placing the addressing
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information on the bus instead of the DMA. This is also
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used to implement a technique known as ``Bus Mastering''.
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When a DMA channel in Cascade Mode receives control
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of the bus, the DMA does not place addresses and I/O
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control signals on the bus like the DMA normally does
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when it is active. Instead, the DMA only asserts the
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-DACK signal for the active DMA channel.
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At this point it is up to the peripheral connected to that
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DMA channel to provide address and bus control signals.
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The peripheral has complete control over the system
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bus, and can do reads and/or writes to any address
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below 16Meg. When the peripheral is finished with
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the bus, it de-asserts the DRQ line, and the DMA
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controller can then return control to the CPU or to some
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other DMA channel.
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Cascade Mode can be used to chain multiple DMA controllers
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together, and this is exactly what DMA Channel 4 is used
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for in the PC architecture. When a peripheral requests
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the bus on DMA channels 0, 1, 2 or 3, the slave DMA
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controller asserts HLDREQ, but this wire is actually connected
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to DRQ4 on the primary DMA controller instead of to the CPU.
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The primary DMA controller, thinking it has work to do on
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Channel 4, requests the bus from the CPU using HLDREQ signal.
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Once the CPU grants the bus to the primary DMA controller,
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-DACK4 is asserted, and that wire is actually connected to
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the HLDA signal on the slave DMA controller. The slave DMA
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controller then transfers data for the DMA channel that
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requested it (0, 1, 2 or 3), or the slave DMA may grant the bus
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to a peripheral that wants to perform its own bus-mastering,
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such as a SCSI controller.
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Because of this wiring arrangement, only DMA channels
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0, 1, 2, 3, 5, 6 and 7 are usable with peripherals on PC/AT
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systems.
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<quote><em>Note:</em> DMA channel 0 was reserved for
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refresh operations in early IBM PC computers, but
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is generally available for use by peripherals in
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modern systems.</quote>
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When a peripheral is performing Bus Mastering, it is
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important that the peripheral transmit data to or
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from memory constantly while it holds the system bus.
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If the peripheral cannot do this, it must release the
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bus frequently so that the system can perform refresh
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operations on main memory.
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The Dynamic RAM used in all PCs for main memory must be
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accessed frequently to keep the bits stored in the
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components "charged". Dynamic RAM essentially consists
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of millions of capacitors with each one holding one bit
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of data. These capacitors are charged with power to
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represent a "1" or drained to represent a "0". Because
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all capacitors leak, power must be added at regular intervals
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to keep the "1" values intact. The RAM chips actually handle
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the task of pumping power back into all of the appropriate
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locations in RAM, but they must be told when to do it by
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the rest of the computer so that the refresh activity won't
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interfere with the computer wanting to access RAM normally.
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If the computer is unable to refresh memory, the contents
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of memory will become corrupted in just a few milliseconds.
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Since memory read and write cycles ``count'' as refresh
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cycles (a dynamic RAM refresh cycle is actually an incomplete
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memory read cycle), as long as the peripheral
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controller continues reading or writing data to
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sequential memory locations, that action will refresh
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all of memory.
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Bus-mastering is found in some SCSI host interfaces and
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other high-performance peripheral controllers.
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<tag>Autoinitialize</tag> This mode causes the DMA to
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perform Byte, Block or Demand transfers, but when the
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DMA transfer counter reaches zero, the counter and
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address are set back to where they were when the DMA
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channel was originally programmed. This means that
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as long as the peripheral requests transfers, they will
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be granted. It is up to the CPU to move new data
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into the fixed buffer ahead of where the DMA is about
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to transfer it when doing output operations, and read new
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data out of the buffer behind where the DMA is writing
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when doing input operations.
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This technique is frequently used on audio devices that
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have small or no hardware ``sample'' buffers. There is
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additional CPU overhead to manage this ``circular'' buffer,
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but in some cases this may be the only way to eliminate the
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latency that occurs when the DMA counter reaches zero
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and the DMA stops transfers until it is reprogrammed.
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</descrip>
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<sect1><heading>Programming the DMA</heading>
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<p>The DMA channel that is to be programmed should always
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be ``masked'' before loading any settings. This is because
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the hardware might unexpectedly assert the DRQ for that channel,
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and the DMA might respond, even though not all of the parameters
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have been loaded or updated.
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Once masked, the host must specify the direction of the
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transfer (memory-to-I/O or I/O-to-memory), what mode of
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DMA operation is to be used for the transfer (Single,
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Block, Demand, Cascade, etc), and finally the address and
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length of the transfer are loaded. The length that is
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loaded is one less than the amount you expect the DMA to
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transfer. The LSB and MSB of the address and length are
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written to the same 8-bit I/O port, so another port must
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be written to first to guarantee that the DMA accepts the
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first byte as the LSB and the second byte as the MSB of
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the length and address.
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Then, be sure to update the Page Register, which is
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external to the DMA and is accessed through a different
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set of I/O ports.
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Once all the settings are ready, the DMA channel can be
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un-masked. That DMA channel is now considered to be
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``armed'', and will respond when the DRQ line for that channel
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is asserted.
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Refer to a hardware data book for precise programming
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details for the 8237. You will also need to refer to the
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I/O port map for the PC system, which describes where
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the DMA and Page Register ports are located. A complete
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port map table is located below.
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<sect1><heading>DMA Port Map</heading>
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<p>All systems based on the IBM-PC and PC/AT have the DMA
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hardware located at the same I/O ports. The complete
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list is provided below. Ports assigned to DMA Controller
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#2 are undefined on non-AT designs.
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<sect2><heading>0x00 - 0x1f DMA Controller #1 (Channels 0, 1, 2 and 3)</heading>
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<p>DMA Address and Count Registers
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<verb>
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0x00 write Channel 0 starting address
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0x00 read Channel 0 current address
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0x01 write Channel 0 starting word count
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0x01 read Channel 0 remaining word count
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0x02 write Channel 1 starting address
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0x02 read Channel 1 current address
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0x03 write Channel 1 starting word count
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0x03 read Channel 1 remaining word count
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0x04 write Channel 2 starting address
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0x04 read Channel 2 current address
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0x05 write Channel 2 starting word count
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0x05 read Channel 2 remaining word count
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0x06 write Channel 3 starting address
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0x06 read Channel 3 current address
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0x07 write Channel 3 starting word count
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0x07 read Channel 3 remaining word count
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</verb>
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DMA Command Registers
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<verb>
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0x08 write Command Register
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0x08 read Status Register
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0x09 write Request Register
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0x09 read -
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0x0a write Single Mask Register Bit
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0x0a read -
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0x0b write Mode Register
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0x0b read -
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0x0c write Clear LSB/MSB Flip-Flop
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0x0c read -
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0x0d write Master Clear/Reset
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0x0d read Temporary Register (not available on newer versions)
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0x0e write Clear Mask Register
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0x0e read -
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0x0f write Write All Mask Register Bits
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0x0f read Read All Mask Register Bits (only in Intel 82374)
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</verb>
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<sect2><heading>0xc0 - 0xdf DMA Controller #2 (Channels 4, 5, 6 and 7)</heading>
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<p>DMA Address and Count Registers
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<verb>
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0xc0 write Channel 4 starting address
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0xc0 read Channel 4 current address
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0xc2 write Channel 4 starting word count
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0xc2 read Channel 4 remaining word count
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0xc4 write Channel 5 starting address
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0xc4 read Channel 5 current address
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|
0xc6 write Channel 5 starting word count
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0xc6 read Channel 5 remaining word count
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|
0xc8 write Channel 6 starting address
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0xc8 read Channel 6 current address
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0xca write Channel 6 starting word count
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0xca read Channel 6 remaining word count
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|
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0xcc write Channel 7 starting address
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0xcc read Channel 7 current address
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0xce write Channel 7 starting word count
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0xce read Channel 7 remaining word count
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|
</verb>
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DMA Command Registers
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<verb>
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|
0xd0 write Command Register
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|
0xd0 read Status Register
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0xd2 write Request Register
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|
0xd2 read -
|
|
0xd4 write Single Mask Register Bit
|
|
0xd4 read -
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|
0xd6 write Mode Register
|
|
0xd6 read -
|
|
0xd8 write Clear LSB/MSB Flip-Flop
|
|
0xd8 read -
|
|
0xda write Master Clear/Reset
|
|
0xda read Temporary Register (not present in Intel 82374)
|
|
0xdc write Clear Mask Register
|
|
0xdc read -
|
|
0xde write Write All Mask Register Bits
|
|
0xdf read Read All Mask Register Bits (only in Intel 82374)
|
|
</verb>
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|
|
|
<sect2><heading>0x80 - 0x9f DMA Page Registers</heading>
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|
|
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<p><verb>
|
|
0x87 r/w Channel 0 Low byte (23-16) page Register
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|
0x83 r/w Channel 1 Low byte (23-16) page Register
|
|
0x81 r/w Channel 2 Low byte (23-16) page Register
|
|
0x82 r/w Channel 3 Low byte (23-16) page Register
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|
|
|
0x8b r/w Channel 5 Low byte (23-16) page Register
|
|
0x89 r/w Channel 6 Low byte (23-16) page Register
|
|
0x8a r/w Channel 7 Low byte (23-16) page Register
|
|
0x8f r/w Low byte page Refresh
|
|
</verb>
|
|
|
|
<sect2><heading>0x400 - 0x4ff 82374 Enhanced DMA Registers</heading>
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|
|
|
<p>
|
|
The Intel 82374 EISA System Component (ESC) was introduced in early 1996
|
|
and includes a DMA controller that provides a superset of 8237 functionality
|
|
as well as other PC-compatible core peripheral components in a single
|
|
package. This chip is targeted at both EISA and PCI platforms, and provides
|
|
modern DMA features like scatter-gather, ring buffers as well as direct
|
|
access by the system DMA to all 32 bits of address space.
|
|
|
|
<p>
|
|
If these features are used, code should also be included to provide similar
|
|
functionality in the previous 16 years worth of PC-compatible computers.
|
|
For compatibility reasons, some of the 82374 registers must be programmed
|
|
<em>after</em> programming the traditional 8237 registers for each
|
|
transfer. Writing to a traditional 8237 register forces the contents
|
|
of some of the 82374 enhanced registers to zero to provide backward
|
|
software compatibility.
|
|
|
|
|
|
<p><verb>
|
|
0x401 r/w Channel 0 High byte (bits 23-16) word count
|
|
0x403 r/w Channel 1 High byte (bits 23-16) word count
|
|
0x405 r/w Channel 2 High byte (bits 23-16) word count
|
|
0x407 r/w Channel 3 High byte (bits 23-16) word count
|
|
0x4c6 r/w Channel 5 High byte (bits 23-16) word count
|
|
0x4ca r/w Channel 6 High byte (bits 23-16) word count
|
|
0x4ce r/w Channel 7 High byte (bits 23-16) word count
|
|
|
|
0x487 r/w Channel 0 High byte (bits 31-24) page Register
|
|
0x483 r/w Channel 1 High byte (bits 31-24) page Register
|
|
0x481 r/w Channel 2 High byte (bits 31-24) page Register
|
|
0x482 r/w Channel 3 High byte (bits 31-24) page Register
|
|
0x48b r/w Channel 5 High byte (bits 31-24) page Register
|
|
0x489 r/w Channel 6 High byte (bits 31-24) page Register
|
|
0x48a r/w Channel 6 High byte (bits 31-24) page Register
|
|
0x48f r/w High byte page Refresh
|
|
|
|
0x4e0 r/w Channel 0 Stop Register (bits 7-2)
|
|
0x4e1 r/w Channel 0 Stop Register (bits 15-8)
|
|
0x4e2 r/w Channel 0 Stop Register (bits 23-16)
|
|
0x4e4 r/w Channel 1 Stop Register (bits 7-2)
|
|
0x4e5 r/w Channel 1 Stop Register (bits 15-8)
|
|
0x4e6 r/w Channel 1 Stop Register (bits 23-16)
|
|
0x4e8 r/w Channel 2 Stop Register (bits 7-2)
|
|
0x4e9 r/w Channel 2 Stop Register (bits 15-8)
|
|
0x4ea r/w Channel 2 Stop Register (bits 23-16)
|
|
0x4ec r/w Channel 3 Stop Register (bits 7-2)
|
|
0x4ed r/w Channel 3 Stop Register (bits 15-8)
|
|
0x4ee r/w Channel 3 Stop Register (bits 23-16)
|
|
0x4f4 r/w Channel 5 Stop Register (bits 7-2)
|
|
0x4f5 r/w Channel 5 Stop Register (bits 15-8)
|
|
0x4f6 r/w Channel 5 Stop Register (bits 23-16)
|
|
0x4f8 r/w Channel 6 Stop Register (bits 7-2)
|
|
0x4f9 r/w Channel 6 Stop Register (bits 15-8)
|
|
0x4fa r/w Channel 6 Stop Register (bits 23-16)
|
|
0x4fc r/w Channel 7 Stop Register (bits 7-2)
|
|
0x4fd r/w Channel 7 Stop Register (bits 15-8)
|
|
0x4fe r/w Channel 7 Stop Register (bits 23-16)
|
|
|
|
0x40a write Channels 0-3 Chaining Mode Register
|
|
0x40a read Channel Interrupt Status Register
|
|
0x4d4 write Channels 4-7 Chaining Mode Register
|
|
0x4d4 read Chaining Mode Status
|
|
0x40c read Chain Buffer Expiration Control Register
|
|
|
|
0x410 write Channel 0 Scatter-Gather Command Register
|
|
0x411 write Channel 1 Scatter-Gather Command Register
|
|
0x412 write Channel 2 Scatter-Gather Command Register
|
|
0x413 write Channel 3 Scatter-Gather Command Register
|
|
0x415 write Channel 5 Scatter-Gather Command Register
|
|
0x416 write Channel 6 Scatter-Gather Command Register
|
|
0x417 write Channel 7 Scatter-Gather Command Register
|
|
|
|
0x418 read Channel 0 Scatter-Gather Status Register
|
|
0x419 read Channel 1 Scatter-Gather Status Register
|
|
0x41a read Channel 2 Scatter-Gather Status Register
|
|
0x41b read Channel 3 Scatter-Gather Status Register
|
|
0x41d read Channel 5 Scatter-Gather Status Register
|
|
0x41e read Channel 5 Scatter-Gather Status Register
|
|
0x41f read Channel 7 Scatter-Gather Status Register
|
|
|
|
0x420-0x423 r/w Channel 0 Scatter-Gather Descriptor Table Pointer Register
|
|
0x424-0x427 r/w Channel 1 Scatter-Gather Descriptor Table Pointer Register
|
|
0x428-0x42b r/w Channel 2 Scatter-Gather Descriptor Table Pointer Register
|
|
0x42c-0x42f r/w Channel 3 Scatter-Gather Descriptor Table Pointer Register
|
|
0x434-0x437 r/w Channel 5 Scatter-Gather Descriptor Table Pointer Register
|
|
0x438-0x43b r/w Channel 6 Scatter-Gather Descriptor Table Pointer Register
|
|
0x43c-0x43f r/w Channel 7 Scatter-Gather Descriptor Table Pointer Register
|
|
</verb>
|
|
|