145 lines
3.7 KiB
Diff
145 lines
3.7 KiB
Diff
--- sys/amd64/amd64/pmap.c.orig
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+++ sys/amd64/amd64/pmap.c
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@@ -1215,6 +1215,9 @@
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vm_size_t s;
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int error, i, pv_npg, ret, skz63;
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+ /* L1TF, reserve page @0 unconditionally */
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+ vm_page_blacklist_add(0, bootverbose);
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+
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/* Detect bare-metal Skylake Server and Skylake-X. */
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if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
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CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
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--- sys/amd64/vmm/intel/vmx.c.orig
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+++ sys/amd64/vmm/intel/vmx.c
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@@ -185,6 +185,12 @@
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SYSCTL_UINT(_hw_vmm_vmx, OID_AUTO, vpid_alloc_failed, CTLFLAG_RD,
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&vpid_alloc_failed, 0, NULL);
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+static int guest_l1d_flush;
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+SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, l1d_flush, CTLFLAG_RD,
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+ &guest_l1d_flush, 0, NULL);
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+
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+uint64_t vmx_msr_flush_cmd;
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+
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/*
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* Use the last page below 4GB as the APIC access address. This address is
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* occupied by the boot firmware so it is guaranteed that it will not conflict
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@@ -720,6 +726,12 @@
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return (error);
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}
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+ guest_l1d_flush = (cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) == 0;
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+ TUNABLE_INT_FETCH("hw.vmm.l1d_flush", &guest_l1d_flush);
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+ if (guest_l1d_flush &&
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+ (cpu_stdext_feature3 & CPUID_STDEXT3_L1D_FLUSH) != 0)
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+ vmx_msr_flush_cmd = IA32_FLUSH_CMD_L1D;
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+
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/*
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* Stash the cr0 and cr4 bits that must be fixed to 0 or 1
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*/
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--- sys/amd64/vmm/intel/vmx_genassym.c.orig
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+++ sys/amd64/vmm/intel/vmx_genassym.c
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@@ -36,6 +36,7 @@
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#include <vm/vm.h>
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#include <vm/pmap.h>
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+#include <vm/vm_param.h>
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#include <machine/vmm.h>
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#include "vmx_cpufunc.h"
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@@ -86,3 +87,6 @@
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ASSYM(KERNEL_SS, GSEL(GDATA_SEL, SEL_KPL));
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ASSYM(KERNEL_CS, GSEL(GCODE_SEL, SEL_KPL));
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+
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+ASSYM(PAGE_SIZE, PAGE_SIZE);
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+ASSYM(KERNBASE, KERNBASE);
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--- sys/amd64/vmm/intel/vmx_support.S.orig
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+++ sys/amd64/vmm/intel/vmx_support.S
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@@ -28,6 +28,7 @@
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*/
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#include <machine/asmacros.h>
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+#include <machine/specialreg.h>
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#include "vmx_assym.h"
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@@ -173,9 +174,47 @@
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jbe invept_error /* Check invept instruction error */
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guest_restore:
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- cmpl $0, %edx
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- je do_launch
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+ /*
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+ * Flush L1D cache if requested. Use IA32_FLUSH_CMD MSR if available,
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+ * otherwise load enough of the data from the zero_region to flush
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+ * existing L1D content.
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+ */
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+#define L1D_FLUSH_SIZE (64 * 1024)
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+ movl %edx, %r8d
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+ cmpb $0, guest_l1d_flush(%rip)
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+ je after_l1d
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+ movq vmx_msr_flush_cmd(%rip), %rax
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+ testq %rax, %rax
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+ jz 1f
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+ movq %rax, %rdx
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+ shrq $32, %rdx
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+ movl $MSR_IA32_FLUSH_CMD, %ecx
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+ wrmsr
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+ jmp after_l1d
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+1: movq $KERNBASE, %r9
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+ movq $-L1D_FLUSH_SIZE, %rcx
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+ /*
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+ * pass 1: Preload TLB.
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+ * Kernel text is mapped using superpages, TLB preload is
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+ * done for the benefit of older CPUs which split 2M page
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+ * into 4k TLB entries.
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+ */
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+2: movb L1D_FLUSH_SIZE(%r9, %rcx), %al
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+ addq $PAGE_SIZE, %rcx
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+ jne 2b
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+ xorl %eax, %eax
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+ cpuid
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+ movq $-L1D_FLUSH_SIZE, %rcx
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+ /* pass 2: Read each cache line */
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+3: movb L1D_FLUSH_SIZE(%r9, %rcx), %al
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+ addq $64, %rcx
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+ jne 3b
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+ lfence
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+#undef L1D_FLUSH_SIZE
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+after_l1d:
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+ cmpl $0, %r8d
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+ je do_launch
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VMX_GUEST_RESTORE
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vmresume
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/*
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--- sys/x86/include/specialreg.h.orig
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+++ sys/x86/include/specialreg.h
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@@ -387,6 +387,7 @@
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*/
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#define CPUID_STDEXT3_IBPB 0x04000000
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#define CPUID_STDEXT3_STIBP 0x08000000
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+#define CPUID_STDEXT3_L1D_FLUSH 0x10000000
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#define CPUID_STDEXT3_ARCH_CAP 0x20000000
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#define CPUID_STDEXT3_SSBD 0x80000000
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@@ -438,6 +439,7 @@
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#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
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#define MSR_MTRRcap 0x0fe
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#define MSR_IA32_ARCH_CAP 0x10a
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+#define MSR_IA32_FLUSH_CMD 0x10b
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#define MSR_BBL_CR_ADDR 0x116
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#define MSR_BBL_CR_DECC 0x118
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#define MSR_BBL_CR_CTL 0x119
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@@ -592,6 +594,9 @@
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/* MSR IA32_PRED_CMD */
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#define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
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+/* MSR IA32_FLUSH_CMD */
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+#define IA32_FLUSH_CMD_L1D 0x00000001
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+
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/*
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* PAT modes.
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*/
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