3571e53040
patches for easier mirroring, to eliminate a special copy, to make www.freebsd.org/security a full copy of security.freebsd.org and be eventually be the same. For now files are just sitting there. The symlinks are missing. Discussed on: www (repository location) Discussed with: simon (so)
208 lines
7.6 KiB
Text
208 lines
7.6 KiB
Text
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AMD Background/Response
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Rich Brunner, AMD Fellow
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AMD appreciates the security community contacting us about
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this issue and giving us a chance to respond. Many thanks to
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Jan Beulich and Andi Kleen for first alerting us to the
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concern around this issue and trying out several solutions.
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Introduction
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============
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To summarize the issue from AMD's perspective, AMD documents
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the operation of the FXSAVE and FXRSTOR instructions as
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follows in the "AMD64 Architecture Programmer's Manual
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Volume 5: 64-Bit Media and x87 Floating-Point Instructions
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Rev 3.06":
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(http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26569.pdf)
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+ FXRSTOR (pg 350):
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"FXRSTOR does not restore the x87 error pointers (last
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instruction pointer, last data pointer, and last
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opcode), except in the relatively rare cases in which
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the exception summary (ES) bit in the x87 status word
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is set to 1, indicating that an unmasked x87 exception
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has occurred."
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+ FXSAVE (pg 352):
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"FXSAVE does not save the x87 pointer registers (last
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instruction pointer, last data pointer, and last
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opcode), except in the relatively rare cases in which
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the exception summary (ES) bit in the x87 status word
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is set to 1, indicating that an unmasked x87 exception
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has occurred."
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AMD purposely designed the implementation of the FXSAVE and
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FXRSTOR instructions in the above manner to significantly
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improve the performance of context-switching. AMD did not
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want to penalize the performance of these instructions for
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all operating systems for the relatively rare case when the
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exception summary bit was set or the unlikely case of the
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x87 exceptions pointers being successfully exploited in a
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real customer environment. Instead, AMD designed the
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instructions to optimize performance for the common case.
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As a result of the operation of FXSAVE and FXRSTOR, it is
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theoretically possible for one process (reader) to observe
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the x87 exception pointers of another process (writer)
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provided that:
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+ no other x87 instructions are executed that affect the
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x87 exception pointers between the time the writer is
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swapped out and the reader is swapped in; and
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+ the reader does not have a pending x87 exception when
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swapped back in; and
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+ the reader does not issue any non-control x87
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instructions when swapped back in before examining x87
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exception pointers.
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Operating systems can employ one of several simple software
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methods to remove the possibility of exploitation as
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described below. In some cases, these methods may actually
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*improve* the performance of an operating-system's
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context-switching code.
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Software Methods
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================
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There are a number of methods, "Clear Sequences", that
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software can use to ensure that the x87 exception pointers
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(ip, dp, opcode) are initialized to benign values on every
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context switch. Below are just a few examples of those
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methods.
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Critical to the first two methods is an OS-dependent "safe
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address": this is some location which can be accessed
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without faulting and whose value is likely in the
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processor's L1 data cache. This location will be loaded into
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the x87 stack to ensure that the x87 exception pointers are
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set to a benign value.
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[Note that the Data Segment Descriptor (DS) that is in
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effect when the kernel executes the clear sequence is
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recorded in the x87 exception pointers. Depending on the OS
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kernel and its mode, this DS may be from the previous
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process. To prevent this, the kernel should ensure that DS
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is loaded with a benign value before executing FXSAVE. For
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example, recent 32-bit Linux kernels already reload DS on
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kernel entry.]
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+ "FXRSTOR-centric" method
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This method sets the x87 exception pointers to a benign
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state just before executing an FXRSTOR. It makes no
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assumption about the state of the current x87 exception
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pointers before executing the restore sequence. In the
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normal case, where ES is not set before the FXRSTOR, the
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"Clear Sequence" takes approximately 14 cycles (as
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measured on an AMD Opteron).
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## Restore Code ...
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## Begin_Clear_Sequence
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fnstsw %ax # Grab x87 ES bit
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ffree st(7) # Clear tag bit to remove
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# -possible stack overflow
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bt $7,%ax # Test ES bit
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jnc 1f # Jump if ES=0
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fnclex # ES=1, so clear it so fild
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# -can't trap
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1: fildl safe_address # Dummy Load from OS-dependent
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# -"safe address" changes all
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# -x87 exception pointers.
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## End_Clear_Sequence
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fxrstor ... # Now swap in process state
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+ "FXSAVE-centric" method
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This method may not apply to all operating systems
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because it requires certain guarantees between FXSAVE
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and a subsequent FXRSTOR; however, this is the method
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that Linux will likely choose. This approach sets the
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x87 exception pointers to a benign state just after
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executing an FXSAVE. Between that point and entry into
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another x87-using process, the requirement is that the
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x87 state remains benign. If anything changes the x87
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exception pointers in the interim, then software must
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clear out or save/restore the state explicitly again
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before executing an FXRSTOR.
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In the normal case, where ES is not set after the
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FXSAVE, the "Clear Sequence" takes approximately 7
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cycles (as measured on an AMD Opteron). However, the
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added cycles to the FXSAVE code may be much less for
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operating systems, like Linux, which currently place an
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unconditional FNCLEX after the FXSAVE. The "Clear
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Sequence" replaces the unconditional FNCLEX with a
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conditional one and may actually *reduce* the number of
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cycles used for the FXSAVE code.
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## FXSAVE Code
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fxsave save_image # save old process state.
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## Begin_Clear_Sequence
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bt $7,save_image.fsw # Test saved ES bit
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jnc 1f # Jump if ES=0
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fnclex # ES=1, so clear it so fild
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# -can't trap
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1: ffree st(7) # Clear tag bit to remove
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# -possible stack overflow
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fildl safe_address # Dummy Load from OS-dependent
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# -"safe address" changes all
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# -x87 exception pointers.
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## End_Clear_Sequence
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...
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## Restore Code
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fxrstor ... # Now swap in process state
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+ FNSAVE and FRSTOR
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32-bit Operating Systems can use FNSAVE and FRSTOR to
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always save and restore the complete x87 execution
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state. However, because these instructions do not
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save/restore XMM registers or associated state, software
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must explicitly perform this operation. In addition,
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because FSAVE/FNSAVE do not save the full 64-bit data
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and instruction pointers for x87 state, 64-bit
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applications should use FXSAVE/FXRSTOR, rather than
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FSAVE/FRSTOR.
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Processors Affected
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===================
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It is AMD's intent that all future "AuthenticAMD" AMD
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processors (those that return "AuthenticAMD" for CPUID
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vendor string) will follow the behavior of FXSAVE and
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FXRSTOR as documented in the "AMD64 Architecture
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Programmer's Manual Volume 5: 64-Bit Media and x87
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Floating-Point Instructions Rev 3.06". In addition, these
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CPUID Families of "AuthenticAMD" AMD processors also follow
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this behavior:
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+ Family=06h: All 7th generation AMD processors (such as
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AMD Athlon, AMD Duron, AMD Athlon MP,
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AMD Athlon XP, and AMD Sempron).
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+ Family=0Fh: All 8th generation AMD processors (such as
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AMD Athlon64, AMD Athlon64 FX, AMD Opteron,
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AMD Turion, and AMD Sempron).
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AMD processors which return "Geode by NSCe" for CPUID vendor
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string do not follow this behavior.
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