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347 lines
8.7 KiB
ArmAsm
347 lines
8.7 KiB
ArmAsm
/* See the end of this file for copyright and license terms. */
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#include <asm/common.h>
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#include <arch/multiboot.h>
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#include <arch/page.h>
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#include <arch/segment.h>
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/*
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* Early boot sequence on amd64.
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*
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* This is loosely based on the 32-bit example code from the OSDev.org wiki:
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* <https://wiki.osdev.org/Higher_Half_x86_Bare_Bones>
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* mixed with some of the Long Mode tutorial code:
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* <https://wiki.osdev.org/Setting_Up_Long_Mode>
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*
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* When entering from the bootloader, we are still in 32-bit protected mode,
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* meaning we have to enable long mode ourselves.
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*
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* Our basic setup procedure is:
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* - set up the stack (unlike on i386, where we do it only as the last step)
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* - perform some sanity checks, like whether the CPU actually supports 64 bits
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* - load the GDT at its *physical* address and use its 32-bit segments
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* - populate the page maps and %cr3 with the 4-level 64-bit structures:
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* + the lowest 1GB (including the entire kernel image) is identity mapped
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* + the same mapping is mirrored to KERNBASE (0xffffffff80000000)
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* + the page tables are mapped recursively at X86_PMAP_OFFSET
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* - enable IA-32e mode by setting IA32_EFER.LME = 1 (see Intel SDM vol 4, tbl 2-2)
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* - enable paging and jump to the higher half mapping
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* - update rsp and rbp to also point to the high address
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* - reload the GDT at its higher half address
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* - discard the identity mapping of low memory
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* - call _boot()
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*/
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.code32 /* we enter in 32-bit protected mode */
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/* from kernel64.ld */
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.extern _image_start_phys
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.extern _image_end_phys
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.extern _boot /* main boot routine -- see ./boot.c */
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/* initial page maps -- see ../mm/amd64/page.c */
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.extern _pml4
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.extern _pdp0
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/* GDT stuff -- see ../mm/segment.S */
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.extern _x86_gdt_desc
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.extern _x86_gdt_desc_phys
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.extern _x86_kern_tss
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.extern _x86_user_tss
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.section .multiboot.text, "ax", @progbits
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/* C code is linked against high memory, this gets the physical address */
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#define PADDR(c_symbol) (c_symbol - KERNBASE)
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/*
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* miscellaneous utility routines
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*/
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/* void fix_tss_base(u64 *gdt_entry, struct x86_tss *tss) */
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L_ENTRY(fix_tss_base)
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movl 4(%esp), %edi
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movl 8(%esp), %eax
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movw %ax, 2(%edi)
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shrl $16, %eax
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movb %al, 4(%edi)
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movb %ah, 7(%edi)
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ret
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L_END(fix_tss_base)
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/* void err_and_hlt(const char *message) */
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L_ENTRY(err_and_hlt)
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mov $0x000b8000, %edx
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mov 4(%esp), %ecx
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movb $0x4f, %ah /* BIOS color code: white text on red background */
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1: movb (%ecx), %al
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testb %al, %al
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jz 2f
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movw %ax, (%edx)
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addl $2, %edx
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incl %ecx
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jmp 1b
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2: cli /* interrupts should already be off, but it won't hurt */
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hlt
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jmp 2b
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L_END(err_and_hlt)
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/*
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* actual setup routine
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*/
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ENTRY(_setup)
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/*
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* set up the stack
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*/
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movl $PADDR(stack_top), %esp
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pushl $0 /* CPU number -- see include/arch/smp.h */
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pushl $0 /* two longwords to keep the stack 8 byte aligned */
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movl %esp, %ebp
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push %ebx /* temporarily stash multiboot tag address away */
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/*
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* the bootloader should have loaded the multiboot magic
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* value into eax, check if that is really the case
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*/
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cmp $MB2_BOOTLOADER_MAGIC, %eax
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je 1f
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pushl $errmsg_no_multiboot
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jmp err_and_hlt
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/*
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* check if the CPU supports the CPUID instruction
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* this is done by checking whether we can flip bit 21 in EFLAGS (??)
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*/
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1: pushf
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pop %eax
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movl %eax, %ecx
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xorl $(1 << 21), %eax
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push %eax
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popf
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pushf
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pop %eax
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push %ecx /* restore original flags */
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popf
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cmp %eax, %ecx
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jne 2f
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pushl $errmsg_no_cpuid
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jmp err_and_hlt
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/*
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* check if the CPU supports extended CPUID addresses
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*/
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2: mov $0x80000000, %eax
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cpuid
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cmp $0x80000001, %eax
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jae 3f
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pushl $errmsg_no_ext_cpuid
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jmp err_and_hlt
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/*
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* check if the CPU supports IA-32e mode
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*/
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3: mov $0x80000001, %eax
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cpuid
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test $(1 << 29), %edx
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jnz 4f
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pushl $errmsg_no_ia32e
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jmp err_and_hlt
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/*
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* load the base values kernel and user TSS into the corresponding GDT entries
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*/
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4: pushl $PADDR(_x86_kern_tss)
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pushl $PADDR(_x86_gdt + X86_KERN_TSS)
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call fix_tss_base
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pushl $PADDR(_x86_user_tss)
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pushl $PADDR(_x86_gdt + X86_USER_TSS)
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call fix_tss_base
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addl $16, %esp
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/*
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* load our own GDT (at its physical address) and its 32-bit segments
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*/
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lgdt _x86_gdt_desc_phys
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ljmp $(X86_32_KERN_CS), $1f
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1: movl $(X86_KERN_DS), %eax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %fs
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movw %ax, %gs
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movw %ax, %ss
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/* XXX do we really need to load a TSS? */
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movl $X86_KERN_TSS, %eax
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ltr %ax
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#if (KERNBASE % (1 << X86_PDP_SHIFT)) != 0
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#error "KERNBASE must be aligned to at least a PDP entry (1 GB)"
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#endif
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#if (X86_PMAP_OFFSET % (1 << X86_PML4_SHIFT)) != 0
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#error "X86_PMAP_OFFSET must be aligned to at least a PML4 entry (512 GB)"
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#endif
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#define V48 0xffff000000000000
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#define PDP_OFFSET(ptr) (( (((ptr) - V48) >> X86_PDP_SHIFT) % 512 ) * 8)
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#define PML4_OFFSET(ptr) ( ((ptr) - V48) >> (X86_PML4_SHIFT) * 8 )
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/*
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* statically map the low 2 GB to itself and to the high kernel half
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*/
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/* for the identity mapping */
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movl $0x00000083, PADDR(_pdp0) /* present (0), write (1), huge (7) */
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movl $0x40000083, PADDR(_pdp0 + 8)
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/* for the -2GB at the end of virtual memory (we use the same PDP for both) */
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movl $0x00000083, PADDR(_pdp0 + PDP_OFFSET(KERNBASE))
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movl $0x40000083, PADDR(_pdp0 + PDP_OFFSET(KERNBASE) + 8)
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movl $PADDR(_pdp0 + 0x003), PADDR(_pml4) /* present (0), write (1), huge (7) */
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movl $PADDR(_pdp0 + 0x003), PADDR(_pml4 + PML4_OFFSET(KERNBASE))
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/* map the PML4 to itself */
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movl $PADDR(_pml4 + 0x003), PADDR(_pml4 + PML4_OFFSET(X86_PMAP_OFFSET))
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movb $0x80, PADDR(_pml4 + PML4_OFFSET(X86_PMAP_OFFSET) + 7) /* NX bit */
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/*
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* ensure paging is disabled by clearing CR0.PG (bit 32)
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*/
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movl %cr0, %eax
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andl $0x7fffffff, %eax
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movl %eax, %cr0
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/*
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* enable:
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* CR4.PSE (Page Size Extensions, bit 4)
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* CR4.PAE (Physical Address Extension, bit 5)
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* CR4.PGE (Page Global Enable, bit 7)
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*/
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movl %cr4, %eax
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orl $0x000000b0, %eax
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movl %eax, %cr4
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/* load cr3 with the PML4 */
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movl $PADDR(_pml4), %eax
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movl %eax, %cr3
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/*
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* enable IA-32e by setting IA32_EFER.LME (bit 8)
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* (and also set No Execute Enable (bit 11) while we're at it)
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*/
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movl $0xc0000080, %ecx
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rdmsr
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orl $0x00000900, %eax
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wrmsr
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/*
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* enable:
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* CR0.PG (Paging, bit31)
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* CR0.WP (Write Protect, bit 16)
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*/
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movl %cr0, %eax
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orl $0x80010000, %eax
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movl %eax, %cr0
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/* remember when we pushed the multiboot tag address stored in ebx
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* like, 100 lines ago? Yeah we restore that now, and put it into
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* the right register to pass it as the first parameter to _boot(). */
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pop %edi
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/* we can't jump to the high half of 64-bit memory directly since this is
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* still a 32-bit instruction, so we need to add an intermediate step to
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* a trampoline which can make the actual 64-bit far jump to high memory */
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ljmpl $X86_64_KERN_CS, $trampoline
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END(_setup)
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/*
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* native 64-bit code starts here
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*/
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.code64
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L_ENTRY(trampoline)
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movabsq $_setup_highmem, %rcx
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jmpq *%rcx
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L_END(trampoline)
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.text
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ASM_ENTRY(_setup_highmem)
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/*
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* update all pointers to virtual address space
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*/
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movabsq $KERNBASE, %rax
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addq %rax, %rsp
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addq %rax, %rbp
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addq %rax, %rdi /* multiboot tag */
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/*
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* reload the GDT, this time with the virtual mapping
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*/
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lgdt _x86_gdt_desc
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/* data segments are ignored in 64-bit mode, load the null descriptor */
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1: xor %eax, %eax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %fs
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movw %ax, %gs
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movw %ax, %ss
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/* reset RFLAGS */
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pushq $0
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popfq
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/* remove the low memory identity mapping and bonk the TLB */
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movl $0, _pdp0
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movl $0, _pdp0 + 8
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movl $0, _pml4
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movq %cr3, %rax
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movq %rax, %cr3
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callq _boot
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/* this should Never Be Reached(TM) */
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cli
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2: hlt
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jmp 2b
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ASM_END(_setup_highmem)
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.section .multiboot.data, "a", @progbits
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L_DATA(errmsg_no_multiboot)
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.asciz "Invalid Multiboot 2 magic number in %eax"
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L_END(errmsg_no_multiboot)
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L_DATA(errmsg_no_cpuid)
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.asciz "CPUID instruction not supported"
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L_END(errmsg_no_cpuid)
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L_DATA(errmsg_no_ext_cpuid)
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.asciz "No extended CPUID features available"
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L_END(errmsg_no_ext_cpuid)
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L_DATA(errmsg_no_ia32e)
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.asciz "CPU does not appear to support IA-32e mode"
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L_END(errmsg_no_ia32e)
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.section .bootstrap_stack, "aw", @nobits
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stack_bottom:
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.skip 16384 /* 16 K for the stack should be plenty for now */
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stack_top:
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/*
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* This file is part of GayBSD.
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* Copyright (c) 2021 fef <owo@fef.moe>.
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*
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* GayBSD is nonviolent software: you may only use, redistribute, and/or
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* modify it under the terms of the Cooperative Nonviolent Public License
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* (CNPL) as found in the LICENSE file in the source code root directory
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* or at <https://git.pixie.town/thufie/npl-builder>; either version 7
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* of the license, or (at your option) any later version.
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*
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* GayBSD comes with ABSOLUTELY NO WARRANTY, to the extent
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* permitted by applicable law. See the CNPL for details.
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*/
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