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195 lines
8.2 KiB
C
195 lines
8.2 KiB
C
/* Copyright (C) 2021,2022 fef <owo@fef.moe>. All rights reserved. */
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#pragma once
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#ifndef _ARCH_PAGE_H_
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#error "This file is not meant to be included directly, use <arch/page.h>"
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#endif
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/*
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* Common abbreviations used throughout the entire x86 vm code base:
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* PT - Page Table
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* PDT - Page Directory Table
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* PDPT - Page Directory Pointer Table
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* PML4T - Page Map Level 4 Table
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* PTE - Page Table Entry
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* PDTE - Page Directory Table Entry
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* PDPTE - Page Directory Pointer Table Entry
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* PML4TE - Page Map Level 4 entry
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* PTI - Page Table Index (range 0 - 511)
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* PDTI - Page Directory Table Index (range 0 - 511)
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* PDPTI - Page Directory Pointer Table Index (range 0 - 511)
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* PML4TI - Page Map Level 4 Index (range 0 - 511)
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*
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* Quick recap on how the x86 transes virtual to physical addresses:
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*
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* |63 48|47 39|38 30|29 21|21 12|11 0|
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* +------------------+-----------+-----------+-----------+-----------+--------------+
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* | 16 bits | 9 bits | 9 bits | 9 bits | 9 bits | 12 bits |
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* +------------------+-----------+-----------+-----------+-----------+--------------+
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* (1) | (copy of bit 47) | PML4T | PDPT | PDT | PT | offset (4 K) |
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* +------------------+-----------+-----------+-----------+-----------+--------------+
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* (2) | (copy of bit 47) | PML4T | PDPT | PDT | offset (2 M) |
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* +------------------+-----------+-----------+-----------+--------------------------+
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* (3) | (copy of bit 47) | PML4T | PDPT | offset (1 G) |
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* +------------------+-----------+-----------+--------------------------------------+
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*
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* %CR3: pointer to PML4T, 256 TB (2^36 pages)
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* PML4T: 512 entries, 512 GB per entry (2^27 pages)
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* PDPT: 512 entries, 1 GB per entry (2^18 pages)
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* PDT: 512 entries, 2 MB per entry (2^9 pages)
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* PT: 512 entries, 4 KB per entry (1 page)
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*
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* PDPT entries can either reference a PDT or a 1 GB region directly (if __P_HUGE is set)
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* PDT entries can either reference a PT or a 2 MB region directly (if __P_HUGE is set)
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*
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* (1) shows a PML4T -> PDPT -> PDT -> PT regular mapping
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* (2) shows a PML4T -> PDPT -> PDT hugepage mapping
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* (3) shows a PML4T -> PDPT gigapage mapping
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*
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* Since the lowest 12 bits are always zero in any page map entry, they are
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* used for flags. Additionally, bit 63 stores the NX (no execute) flag.
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*/
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#include <arch/vmparam.h>
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#define X86_PT_SHIFT PAGE_SHIFT
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#define X86_PDT_SHIFT (X86_PT_SHIFT + 9)
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#define X86_PDPT_SHIFT (X86_PDT_SHIFT + 9)
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#define X86_PML4T_SHIFT (X86_PDPT_SHIFT + 9)
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#define __HAVE_NOEXEC
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#define __HAVE_GIGAPAGES
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/** @brief Binary logarithm of `HUGEPAGE_SIZE`. */
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#define HUGEPAGE_SHIFT X86_PDT_SHIFT
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/** @brief Binary logarithm of `GIGAPAGE_SIZE`. */
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#define GIGAPAGE_SHIFT X86_PDPT_SHIFT
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#ifndef _ASM_SOURCE
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#include <gay/cdefs.h>
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#include <gay/types.h>
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/**
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* @brief A single 64-bit page map entry, split up into its individual bit flags.
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* The layout matches that of the Intel SDM, vol 3, sect 4.3, fig 4-4.
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*/
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struct x86_pmap_flags {
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/* 0 */bool present:1; /**< Page Fault on access if 0 */
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/* 1 */bool rw:1; /**< Page Fault on write if 0 */
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/* 2 */bool user:1; /**< Page Fault on user mode access if 0 */
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/* 3 */bool write_through:1; /**< Enable write-through caching */
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/* 4 */bool cache_disabled:1; /**< Disable caching in TLB */
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/* 5 */bool accessed:1; /**< 1 if page has been accessed */
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/* 6 */bool dirty:1; /**< 1 if page has been written to */
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/* 7 */bool huge:1; /**< Only valid for PDPTEs and PDTEs */
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/* 8 */bool global:1; /**< Entry survives `vm_flush()` if 1 */
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/* 9 */unsigned _unused:3;
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/* 12 */vm_paddr_t shifted_address:51;
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/* 63 */bool noexec:1; /**< Prevent instruction fetches */
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} __packed;
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/* bitmasks for the structure above */
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#define __P_PRESENT (1 << 0)
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#define __P_RW (1 << 1)
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#define __P_USER (1 << 2)
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#define __P_WRITE_THROUGH (1 << 3)
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#define __P_NOCACHE (1 << 4)
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#define __P_ACCESSED (1 << 5)
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#define __P_DIRTY (1 << 6)
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#define __P_HUGE (1 << 7)
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#define __P_GLOBAL (1 << 8)
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#define __P_SLAB (1 << 9)
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#define __P_ATOMIC (1 << 10)
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#define __P_NOEXEC (1ul << 63)
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/** @brief Bitmask for extracting the physical address from a page map entry. */
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#define X86_PMAP_MASK 0x7ffffffffffff000
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/*
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* these types are deliberately not merged into one so that the
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* compiler can catch accidental assignments to the wrong type
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*/
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#define __pmap_entry_union union { \
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struct x86_pmap_flags flags; \
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vm_paddr_t val; \
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}
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/** @brief x86 Page Table Entry. */
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typedef __pmap_entry_union x86_pte_t;
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/** @brief x86 Page Directory Table Entry. */
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typedef __pmap_entry_union x86_pdte_t;
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/** @brief x86 Page Directory Pointer Table Entry. */
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typedef __pmap_entry_union x86_pdpte_t;
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/** @brief x86 Page Map Level 4 Table Entry. */
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typedef __pmap_entry_union x86_pml4te_t;
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/** @brief x86 Page Table. */
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typedef struct { x86_pte_t entries[512]; } __aligned(PAGE_SIZE) x86_pt_t;
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/** @brief x86 Page Directory Table. */
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typedef struct { x86_pdte_t entries[512]; } __aligned(PAGE_SIZE) x86_pdt_t;
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/** @brief x86 Page Directory Pointer Table. */
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typedef struct { x86_pdpte_t entries[512]; } __aligned(PAGE_SIZE) x86_pdpt_t;
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/** @brief x86 Page Map Level 4 Table. */
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typedef struct { x86_pml4te_t entries[512]; } __aligned(PAGE_SIZE) x86_pml4t_t;
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/* you aren't expected to understand any of these, they're just nasty offset calculations */
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#define __V48_MASK ( ((uintptr_t)1 << 48) - 1 )
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/** @brief Get the linear 48-bit address */
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#define __V48(ptr) ((uintptr_t)(ptr) & __V48_MASK)
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/**
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* @brief Generate a 48-bit virtual address in user space, based on its pmap indices.
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* Every index must be less than 512, or you'll get a garbage address.
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* `pml4i` must be less than 256, or you'll hurt the MMU's feelings.
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* This is because bits 63-48 of the virtual address must all match bit 47.
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*/
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#define UV48ADDR(pml4ti, pdpti, pdti, pti) ( \
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(vm_paddr_t)(pml4ti) << X86_PML4T_SHIFT | \
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(vm_paddr_t)(pdpti) << X86_PDPT_SHIFT | \
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(vm_paddr_t)(pdti) << X86_PDT_SHIFT | \
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(vm_paddr_t)(pti) << X86_PT_SHIFT \
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)
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/**
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* @brief Generate a 48-bit virtual address in kernel space, based on its pmap indices.
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* Every index must be less than 512, or you'll get a garbage address.
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* `pml4i` must be at least 256, or you'll hurt the MMU's feelings.
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* This is because bits 63-48 of the virtual address must all match bit 47.
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*/
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#define KV48ADDR(pml4ti, pdpti, pdti, pti) ( \
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(vm_paddr_t)0xffff000000000000 | \
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UV48ADDR(pml4ti, pdpti, pdti, pti) \
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)
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/** @brief Get the Page Table index for a given virtual address. */
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#define X86_PTI(ptr) ((__V48(ptr) >> X86_PT_SHIFT ) % 512)
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/** @brief Get the Page Directory Table index for a given virtual address. */
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#define X86_PDTI(ptr) ((__V48(ptr) >> X86_PDT_SHIFT ) % 512)
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/** @brief Get the Page Directory Pointer Table index for a given virtual address. */
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#define X86_PDPTI(ptr) ((__V48(ptr) >> X86_PDPT_SHIFT ) % 512)
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/** @brief Get the Page Map Level 4 Table index for a given virtual address. */
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#define X86_PML4TI(ptr) (__V48(ptr) >> X86_PML4T_SHIFT)
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/* Page Map Level 4 Table index for the recursive page map */
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#define __PML4TI (X86_PML4TI(X86_PMAP_OFFSET)) /* = 256 */
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#define __PT_BASE ( (x86_pt_t *)KV48ADDR(__PML4TI, 0, 0, 0) )
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#define __PDT_BASE ( (x86_pdt_t *)KV48ADDR(__PML4TI, __PML4TI, 0, 0) )
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#define __PDPT_BASE ( (x86_pdpt_t *)KV48ADDR(__PML4TI, __PML4TI, __PML4TI, 0) )
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#define __PML4T_BASE ( (x86_pml4t_t *)KV48ADDR(__PML4TI, __PML4TI, __PML4TI, __PML4TI) )
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/** @brief Get the Page Table Entry for a given virtual address. */
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#define X86_PTE(ptr) ( &__PT_BASE->entries[__V48(ptr) >> X86_PT_SHIFT] )
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/** @brief Get the Page Directory Table Entry for a given virtual address. */
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#define X86_PDTE(ptr) ( &__PDT_BASE->entries[__V48(ptr) >> X86_PDT_SHIFT] )
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/** @brief Get the Page Directory Pointer Table Entry for a given virtual address. */
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#define X86_PDPTE(ptr) ( &__PDPT_BASE->entries[__V48(ptr) >> X86_PDPT_SHIFT] )
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/** @brief Get the Page Map Level 4 Table Entry for a given virtual address. */
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#define X86_PML4TE(ptr) ( &__PML4T_BASE->entries[__V48(ptr) >> X86_PML4T_SHIFT] )
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#endif /* not _ASM_SOURCE */
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