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66 lines
2.0 KiB
ArmAsm
66 lines
2.0 KiB
ArmAsm
/* Copyright (C) 2021,2022 fef <owo@fef.moe>. All rights reserved. */
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#include <arch/segment.h>
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#include <arch/vmparam.h>
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#include <asm/common.h>
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.section .multiboot.data, "a", @progbits
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.align 8
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.long 0
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.word 0
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DATA(_x86_gdt_desc_phys)
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.word _x86_gdt_end - _x86_gdt - 1 /* limit */
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.quad _x86_gdt - KERNBASE /* base */
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END(_x86_gdt_desc_phys)
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.data
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.align 8
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.long 0 /* padding */
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.word 0 /* another padding :) */
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DATA(_x86_gdt_desc)
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.word _x86_gdt_end - _x86_gdt - 1 /* limit */
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.quad _x86_gdt /* base */
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END(_x86_gdt_desc)
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/*
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* These entries were generated using the GDT generator tool in
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* arch/x86/tools/gdt.c and are the same on both i386 and amd64.
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*
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* AMD did the only sane thing and reduced segmentation to its minimum
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* in 64-bit mode, where the base and limit values are ignored (64-bit
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* segments always refer to the entire linear memory). They still have
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* their base and limit set to the entire 32-bit address space though,
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* because the CPU makes one last 32-bit segment check when jumping
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* from 32-bit to 64-bit mode.
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*
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* The base values for the two TSS entries are inserted in the assembly
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* setup routine (see arch/x86/boot/setup{32,64}.S).
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*/
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.align 8
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DATA(_x86_gdt)
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.quad 0x0000000000000000 /* 0x00 null descriptor */
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.quad 0x0000000000000000 /* 0x08 unused */
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.quad 0x00cf9a000000ffff /* 0x10 kernel code 32-bit */
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.quad 0x00cffa000000ffff /* 0x18 user code 32-bit */
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.quad 0x00af9a000000ffff /* 0x20 kernel code 64-bit */
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.quad 0x00affa000000ffff /* 0x28 user code 64-bit */
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.quad 0x00cf92000000ffff /* 0x30 kernel data */
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.quad 0x00cff2000000ffff /* 0x38 user data */
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.quad 0x0040890000000068 /* 0x40 kernel TSS */
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.quad 0x0000000000000000 /* 0x48 .. pad for 64-bit */
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.quad 0x0040e90000000068 /* 0x50 user TSS */
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.quad 0x0000000000000000 /* 0x58 .. pad for 64-bit */
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END(_x86_gdt)
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DATA(_x86_gdt_end)
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END(_x86_gdt_end)
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DATA(_x86_kern_tss)
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.skip 0x68
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END(_x86_kern_tss)
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DATA(_x86_user_tss)
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.skip 0x68
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END(_x86_user_tss)
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