arch: add fault handlers, rename exceptions
This commit is contained in:
parent
7fa55c8dab
commit
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GPG key ID:
EC22E476DC2D3D84
9 changed files with 368 additions and 141 deletions
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@ -16,9 +16,11 @@ target_sources(ardix_arch PRIVATE
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atom.c
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atomic.c
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entry.c
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handle_fault.c
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handle_fault.S
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handle_pend_sv.S
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handle_svc.S
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interrupt.c
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irq_pend_sv.S
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irq_svc.S
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mutex.S
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sched.c
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serial.c
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53
arch/at91sam3x8e/handle_fault.S
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53
arch/at91sam3x8e/handle_fault.S
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@ -0,0 +1,53 @@
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/* See the end of this file for copyright, license, and warranty information. */
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/*
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* See arch_handle_fault()
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*/
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.include "asm.S"
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.text
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/* __naked __noreturn void arch_handle_fault(struct reg_snapshot *regs, int irqnum); */
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.extern arch_handle_fault
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func_begin handle_hard_fault
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push {r4-r11,lr}
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mov r0, sp
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mov r1, #0xfffffff3 /* -13 */
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b arch_handle_fault
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func_end handle_hard_fault
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func_begin handle_mm_fault
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push {r4-r11,lr}
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mov r0, sp
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mov r1, #0xfffffff4 /* -12 */
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b arch_handle_fault
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func_end handle_mm_fault
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func_begin handle_bus_fault
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push {r4-r11,lr}
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mov r0, sp
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mov r1, #0xfffffff5 /* -11 */
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b arch_handle_fault
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func_end handle_bus_fault
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func_begin handle_usage_fault
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push {r4-r11,lr}
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mov r0, sp
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mov r1, #0xfffffff6 /* -10 */
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b arch_handle_fault
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func_end handle_usage_fault
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/*
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* This file is part of Ardix.
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* Copyright (c) 2020, 2021 Felix Kopp <owo@fef.moe>.
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*
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* Ardix is non-violent software: you may only use, redistribute,
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* and/or modify it under the terms of the CNPLv6+ as found in
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* the LICENSE file in the source code root directory or at
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* <https://git.pixie.town/thufie/CNPL>.
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*
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* Ardix comes with ABSOLUTELY NO WARRANTY, to the extent
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* permitted by applicable law. See the CNPLv6+ for details.
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*/
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168
arch/at91sam3x8e/handle_fault.c
Normal file
168
arch/at91sam3x8e/handle_fault.c
Normal file
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@ -0,0 +1,168 @@
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/* See the end of this file for copyright, license, and warranty information. */
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#include <arch-generic/hardware.h>
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#include <arch/hardware.h>
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#include <arch/interrupt.h>
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#include <toolchain.h>
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/** Setup UART to manual byte-by-byte control */
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static inline void uart_emergency_setup(void)
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{
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REG_UART_PDC_PTCR = REG_UART_PDC_PTCR_RXTDIS_MASK | REG_UART_PDC_PTCR_TXTDIS_MASK;
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REG_UART_CR = REG_UART_CR_RXDIS_MASK | REG_UART_CR_RSTRX_MASK
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| REG_UART_CR_TXDIS_MASK | REG_UART_CR_RSTTX_MASK;
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REG_UART_IDR = 0xffffffff;
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REG_UART_CR = REG_UART_CR_RXEN_MASK | REG_UART_CR_TXEN_MASK;
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}
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static void uart_write_sync(const char *s)
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{
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char c;
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while ((c = *s++) != '\0') {
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mom_are_we_there_yet(REG_UART_SR & REG_UART_SR_TXRDY_MASK);
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REG_UART_THR = c;
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}
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}
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wswitch"
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static inline void print_err_msg(enum irqno irqno)
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{
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switch (irqno) {
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case IRQNO_HARD_FAULT:
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uart_write_sync("Hard");
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break;
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case IRQNO_MM_FAULT:
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uart_write_sync("Memory Management");
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break;
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case IRQNO_BUS_FAULT:
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uart_write_sync("Bus");
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break;
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case IRQNO_USAGE_FAULT:
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uart_write_sync("Usage");
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break;
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}
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uart_write_sync(" Fault encountered, system halted.\n\n");
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}
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#pragma GCC diagnostic pop /* -Wswitch */
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static void reg_to_str(char *dest, uint32_t val)
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{
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for (int i = 28; i >= 0; i -= 4) {
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uint8_t digit = (val >> i) & 0x0f;
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if (digit < 0x0a)
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digit += '0';
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else
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digit += 'a';
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*dest++ = digit;
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}
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}
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static void print_regs(struct reg_snapshot *regs)
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{
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static char reg_line[] = "r0 = 0x????????\n";
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char *reg_val = ®_line[8]; /* first question mark */
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reg_to_str(reg_val, regs->hw.r0);
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uart_write_sync(reg_line);
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reg_line[1] = '1';
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reg_to_str(reg_val, regs->hw.r1);
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uart_write_sync(reg_line);
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reg_line[1] = '2';
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reg_to_str(reg_val, regs->hw.r2);
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uart_write_sync(reg_line);
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reg_line[1] = '3';
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reg_to_str(reg_val, regs->hw.r3);
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uart_write_sync(reg_line);
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reg_line[1] = '4';
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reg_to_str(reg_val, regs->sw.r4);
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uart_write_sync(reg_line);
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reg_line[1] = '5';
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reg_to_str(reg_val, regs->sw.r5);
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uart_write_sync(reg_line);
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reg_line[1] = '6';
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reg_to_str(reg_val, regs->sw.r6);
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uart_write_sync(reg_line);
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reg_line[1] = '7';
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reg_to_str(reg_val, regs->sw.r7);
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uart_write_sync(reg_line);
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reg_line[1] = '8';
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reg_to_str(reg_val, regs->sw.r8);
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uart_write_sync(reg_line);
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reg_line[1] = '9';
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reg_to_str(reg_val, regs->sw.r9);
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uart_write_sync(reg_line);
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reg_line[1] = '1';
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reg_line[2] = '0';
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reg_to_str(reg_val, regs->sw.r10);
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uart_write_sync(reg_line);
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reg_line[2] = '1';
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reg_to_str(reg_val, regs->sw.r11);
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uart_write_sync(reg_line);
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reg_line[2] = '2';
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reg_to_str(reg_val, regs->hw.r12);
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uart_write_sync(reg_line);
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reg_line[0] = 's';
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reg_line[1] = 'p';
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reg_line[2] = ' ';
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reg_to_str(reg_val, (uint32_t)(regs + 1)); /* where SP was before reg save */
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uart_write_sync(reg_line);
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reg_line[0] = 'l';
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reg_line[1] = 'r';
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reg_to_str(reg_val, (uint32_t)regs->hw.lr);
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uart_write_sync(reg_line);
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reg_line[0] = 'p';
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reg_line[1] = 'c';
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reg_to_str(reg_val, (uint32_t)regs->hw.pc);
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uart_write_sync(reg_line);
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}
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#include <arch/debug.h>
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__naked __noreturn void arch_handle_fault(struct reg_snapshot *regs, enum irqno irqno)
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{
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uart_emergency_setup();
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print_err_msg(irqno);
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print_regs(regs);
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/* give developers a chance to inspect the system */
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__breakpoint;
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/* but never leave this function */
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while (1);
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}
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/*
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* This file is part of Ardix.
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* Copyright (c) 2020, 2021 Felix Kopp <owo@fef.moe>.
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*
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* Ardix is non-violent software: you may only use, redistribute,
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* and/or modify it under the terms of the CNPLv6+ as found in
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* the LICENSE file in the source code root directory or at
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* <https://git.pixie.town/thufie/CNPL>.
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*
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* Ardix comes with ABSOLUTELY NO WARRANTY, to the extent
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* permitted by applicable law. See the CNPLv6+ for details.
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*/
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@ -6,8 +6,8 @@
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.extern sched_process_switch
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/* void irq_pend_sv(void); */
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func_begin irq_pend_sv
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/* void handle_pend_sv(void); */
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func_begin handle_pend_sv
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/*
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* Some registers have already been saved by hardware at this point,
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* we only need to take care of r4-r11 and lr (the latter of which is
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@ -40,7 +40,7 @@ func_begin irq_pend_sv
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bx lr
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func_end irq_pend_sv
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func_end handle_pend_sv
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/*
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* This file is part of Ardix.
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@ -6,8 +6,8 @@
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.extern arch_enter
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/* void irq_svc(void); */
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func_begin irq_svc
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/* void handle_svc(void); */
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func_begin handle_svc
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/*
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* Syscalls on Cortex-M use the following parameter calling convention:
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*
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@ -34,7 +34,7 @@ func_begin irq_svc
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bx lr
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func_end irq_svc
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func_end handle_svc
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/*
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* This file is part of Ardix.
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@ -2,26 +2,26 @@
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#pragma once
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/** Reset interrupt handler */
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void irq_reset(void);
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/** Reset exception handler */
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void handle_reset(void);
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/** Non-maskable interrupt handler */
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void irq_nmi(void);
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/** Hard fault inerrupt handler */
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void irq_hard_fault(void);
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/** Memory management fault interrupt handler */
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void irq_mem_fault(void);
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/** Bus fault interrupt handler */
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void irq_bus_fault(void);
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/** Usage fault (illegal instruction) interrupt handler */
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void irq_usage_fault(void);
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/** SVC interrupt handler */
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void irq_svc(void);
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void handle_nmi(void);
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/** Hard fault exception handler */
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void handle_hard_fault(void);
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/** Memory management fault exception handler */
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void handle_mem_fault(void);
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/** Bus fault exception handler */
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void handle_bus_fault(void);
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/** Usage fault exception handler */
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void handle_usage_fault(void);
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/** SVC exception handler */
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void handle_svc(void);
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/** Debug handler (reserved) */
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void irq_debug_mon(void);
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/** Pending SV interrupt handler */
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void irq_pend_sv(void);
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/** SysTick interrupt handler */
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void irq_sys_tick(void);
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void handle_debug_mon(void);
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/** PendSV interrupt handler */
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void handle_pend_sv(void);
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/** SysTick exception handler */
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void handle_sys_tick(void);
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/** Supply Controller (0) interrupt handler */
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void irq_supc(void);
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@ -107,11 +107,14 @@ void irq_can0(void);
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void irq_can1(void);
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/**
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* Interrupt numbers for sam3x8e
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* @brief IRQ numbers for sam3x8e.
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*
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* Like CMSIS, we treat other exceptions basically the same as IRQs.
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*/
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enum irqno {
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IRQNO_NMI = -14,
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IRQNO_MEM_FAULT = -12,
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IRQNO_HARD_FAULT = -13,
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IRQNO_MM_FAULT = -12,
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IRQNO_BUS_FAULT = -11,
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IRQNO_USAGE_FAULT = -10,
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IRQNO_SVC_CALL = -5,
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@ -9,10 +9,10 @@
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#include <string.h>
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void irq_sys_tick(void)
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void handle_sys_tick(void)
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{
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/*
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* fire a PendSV interrupt and do the actual context switching there
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* fire a PendSV exception and do the actual context switching there
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* because it is faster that way (according to the docs, at least)
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*/
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if (!is_atomic_context())
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@ -68,7 +68,7 @@ void arch_sched_task_init(struct task *task, void (*entry)(void))
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void yield(enum task_state state)
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{
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REG_SYSTICK_VAL = 0U; /* Reset timer */
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REG_SYSTICK_VAL = 0U; /* Reset timer (TODO: don't do this lmao) */
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current->state = state;
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arch_irq_invoke(IRQNO_PEND_SV);
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}
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@ -27,7 +27,7 @@ extern uint32_t _eheap; /* heap end */
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/* implementation in init/main.c */
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extern int main(void);
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__naked void irq_reset(void)
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__naked __noreturn void handle_reset(void)
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{
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sys_init();
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@ -45,133 +45,129 @@ __naked void irq_reset(void)
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}
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/**
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* Default IRQ for unimplemented interrupts.
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* Default handler for unimplemented interrupts.
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* This will halt the system.
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*/
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void irq_stub(void)
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void _stub_handler(void)
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{
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while (1);
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}
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__weak __alias(irq_stub) void irq_nmi(void);
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__weak __alias(irq_stub) void irq_hard_fault(void);
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__weak __alias(irq_stub) void irq_mem_fault(void);
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__weak __alias(irq_stub) void irq_bus_fault(void);
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__weak __alias(irq_stub) void irq_usage_fault(void);
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__weak __alias(irq_stub) void irq_svc(void);
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__weak __alias(irq_stub) void irq_debug_mon(void);
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__weak __alias(irq_stub) void irq_pend_sv(void);
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__weak __alias(irq_stub) void irq_sys_tick(void);
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void handle_nmi(void) __weak __alias(_stub_handler);
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void handle_hard_fault(void) __weak __alias(_stub_handler);
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void handle_mm_fault(void) __weak __alias(_stub_handler);
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void handle_bus_fault(void) __weak __alias(_stub_handler);
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void handle_usage_fault(void) __weak __alias(_stub_handler);
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void handle_svc(void) __weak __alias(_stub_handler);
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void handle_debug_mon(void) __weak __alias(_stub_handler);
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void handle_pend_sv(void) __weak __alias(_stub_handler);
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void handle_sys_tick(void) __weak __alias(_stub_handler);
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__weak __alias(irq_stub) void irq_supc(void);
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__weak __alias(irq_stub) void irq_rstc(void);
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__weak __alias(irq_stub) void irq_rtc(void);
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__weak __alias(irq_stub) void irq_rtt(void);
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__weak __alias(irq_stub) void irq_wdt(void);
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__weak __alias(irq_stub) void irq_pmc(void);
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__weak __alias(irq_stub) void irq_efc0(void);
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__weak __alias(irq_stub) void irq_efc1(void);
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__weak __alias(irq_stub) void irq_uart(void);
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__weak __alias(irq_stub) void irq_smc(void);
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__weak __alias(irq_stub) void irq_pioa(void);
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__weak __alias(irq_stub) void irq_piob(void);
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__weak __alias(irq_stub) void irq_pioc(void);
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__weak __alias(irq_stub) void irq_piod(void);
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__weak __alias(irq_stub) void irq_usart0(void);
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__weak __alias(irq_stub) void irq_usart1(void);
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__weak __alias(irq_stub) void irq_usart2(void);
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__weak __alias(irq_stub) void irq_usart3(void);
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__weak __alias(irq_stub) void irq_hsmci(void);
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__weak __alias(irq_stub) void irq_twi0(void);
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__weak __alias(irq_stub) void irq_twi1(void);
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__weak __alias(irq_stub) void irq_spi0(void);
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__weak __alias(irq_stub) void irq_ssc(void);
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__weak __alias(irq_stub) void irq_tc0(void);
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__weak __alias(irq_stub) void irq_tc1(void);
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__weak __alias(irq_stub) void irq_tc2(void);
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__weak __alias(irq_stub) void irq_tc3(void);
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__weak __alias(irq_stub) void irq_tc4(void);
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__weak __alias(irq_stub) void irq_tc5(void);
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__weak __alias(irq_stub) void irq_tc6(void);
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__weak __alias(irq_stub) void irq_tc7(void);
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__weak __alias(irq_stub) void irq_tc8(void);
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__weak __alias(irq_stub) void irq_pwm(void);
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__weak __alias(irq_stub) void irq_adc(void);
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__weak __alias(irq_stub) void irq_dacc(void);
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__weak __alias(irq_stub) void irq_dmac(void);
|
||||
__weak __alias(irq_stub) void irq_uotghs(void);
|
||||
__weak __alias(irq_stub) void irq_trng(void);
|
||||
__weak __alias(irq_stub) void irq_emac(void);
|
||||
__weak __alias(irq_stub) void irq_can0(void);
|
||||
__weak __alias(irq_stub) void irq_can1(void);
|
||||
void irq_supc(void) __weak __alias(_stub_handler);
|
||||
void irq_rstc(void) __weak __alias(_stub_handler);
|
||||
void irq_rtc(void) __weak __alias(_stub_handler);
|
||||
void irq_rtt(void) __weak __alias(_stub_handler);
|
||||
void irq_wdt(void) __weak __alias(_stub_handler);
|
||||
void irq_pmc(void) __weak __alias(_stub_handler);
|
||||
void irq_efc0(void) __weak __alias(_stub_handler);
|
||||
void irq_efc1(void) __weak __alias(_stub_handler);
|
||||
void irq_uart(void) __weak __alias(_stub_handler);
|
||||
void irq_smc(void) __weak __alias(_stub_handler);
|
||||
void irq_pioa(void) __weak __alias(_stub_handler);
|
||||
void irq_piob(void) __weak __alias(_stub_handler);
|
||||
void irq_pioc(void) __weak __alias(_stub_handler);
|
||||
void irq_piod(void) __weak __alias(_stub_handler);
|
||||
void irq_usart0(void) __weak __alias(_stub_handler);
|
||||
void irq_usart1(void) __weak __alias(_stub_handler);
|
||||
void irq_usart2(void) __weak __alias(_stub_handler);
|
||||
void irq_usart3(void) __weak __alias(_stub_handler);
|
||||
void irq_hsmci(void) __weak __alias(_stub_handler);
|
||||
void irq_twi0(void) __weak __alias(_stub_handler);
|
||||
void irq_twi1(void) __weak __alias(_stub_handler);
|
||||
void irq_spi0(void) __weak __alias(_stub_handler);
|
||||
void irq_ssc(void) __weak __alias(_stub_handler);
|
||||
void irq_tc0(void) __weak __alias(_stub_handler);
|
||||
void irq_tc1(void) __weak __alias(_stub_handler);
|
||||
void irq_tc2(void) __weak __alias(_stub_handler);
|
||||
void irq_tc3(void) __weak __alias(_stub_handler);
|
||||
void irq_tc4(void) __weak __alias(_stub_handler);
|
||||
void irq_tc5(void) __weak __alias(_stub_handler);
|
||||
void irq_tc6(void) __weak __alias(_stub_handler);
|
||||
void irq_tc7(void) __weak __alias(_stub_handler);
|
||||
void irq_tc8(void) __weak __alias(_stub_handler);
|
||||
void irq_pwm(void) __weak __alias(_stub_handler);
|
||||
void irq_adc(void) __weak __alias(_stub_handler);
|
||||
void irq_dacc(void) __weak __alias(_stub_handler);
|
||||
void irq_dmac(void) __weak __alias(_stub_handler);
|
||||
void irq_uotghs(void) __weak __alias(_stub_handler);
|
||||
void irq_trng(void) __weak __alias(_stub_handler);
|
||||
void irq_emac(void) __weak __alias(_stub_handler);
|
||||
void irq_can0(void) __weak __alias(_stub_handler);
|
||||
void irq_can1(void) __weak __alias(_stub_handler);
|
||||
|
||||
__section(.vectors) const void *exception_table[] = {
|
||||
&_estack, /* initial SP value (stack grows down) */
|
||||
&irq_reset, /* reset vector */
|
||||
handle_reset, /* reset vector */
|
||||
NULL, /* reserved */
|
||||
&irq_hard_fault, /* hard fault */
|
||||
&irq_mem_fault, /* memory management fault */
|
||||
&irq_bus_fault, /* bus fault */
|
||||
&irq_usage_fault, /* usage fault */
|
||||
handle_hard_fault, /* hard fault */
|
||||
handle_mm_fault, /* memory management fault */
|
||||
handle_bus_fault, /* bus fault */
|
||||
handle_usage_fault, /* usage fault */
|
||||
NULL, /* reserved */
|
||||
NULL, /* reserved */
|
||||
NULL, /* reserved */
|
||||
NULL, /* reserved */
|
||||
&irq_svc, /* SVC call (used for syscalls) */
|
||||
&irq_debug_mon, /* reserved for debug */
|
||||
handle_svc, /* SVC call (used for syscalls) */
|
||||
handle_debug_mon, /* reserved for debug */
|
||||
NULL, /* reserved */
|
||||
&irq_pend_sv, /* PendSV (used by the scheduler) */
|
||||
&irq_sys_tick, /* SysTick */
|
||||
handle_pend_sv, /* PendSV (used by the scheduler) */
|
||||
handle_sys_tick, /* SysTick */
|
||||
|
||||
/*
|
||||
* Ok I am REALLY tired of writing out mnemonics.
|
||||
* Just have a look at include/arch/at91sam3x8e.h for details.
|
||||
*/
|
||||
&irq_supc,
|
||||
&irq_rstc,
|
||||
&irq_rtc,
|
||||
&irq_rtt,
|
||||
&irq_wdt,
|
||||
&irq_pmc,
|
||||
&irq_efc0,
|
||||
&irq_efc1,
|
||||
&irq_uart,
|
||||
&irq_smc,
|
||||
irq_supc,
|
||||
irq_rstc,
|
||||
irq_rtc,
|
||||
irq_rtt,
|
||||
irq_wdt,
|
||||
irq_pmc,
|
||||
irq_efc0,
|
||||
irq_efc1,
|
||||
irq_uart,
|
||||
irq_smc,
|
||||
NULL, /* reserved */
|
||||
&irq_pioa,
|
||||
&irq_piob,
|
||||
&irq_pioc,
|
||||
&irq_piod,
|
||||
irq_pioa,
|
||||
irq_piob,
|
||||
irq_pioc,
|
||||
irq_piod,
|
||||
NULL, /* reserved */
|
||||
NULL, /* reserved */
|
||||
&irq_usart0,
|
||||
&irq_usart1,
|
||||
&irq_usart2,
|
||||
&irq_usart3,
|
||||
&irq_hsmci,
|
||||
&irq_twi0,
|
||||
&irq_twi1,
|
||||
&irq_spi0,
|
||||
irq_usart0,
|
||||
irq_usart1,
|
||||
irq_usart2,
|
||||
irq_usart3,
|
||||
irq_hsmci,
|
||||
irq_twi0,
|
||||
irq_twi1,
|
||||
irq_spi0,
|
||||
NULL, /* reserved */
|
||||
&irq_ssc,
|
||||
&irq_tc0,
|
||||
&irq_tc1,
|
||||
&irq_tc2,
|
||||
&irq_tc3,
|
||||
&irq_tc4,
|
||||
&irq_tc5,
|
||||
&irq_tc6,
|
||||
&irq_tc7,
|
||||
&irq_tc8,
|
||||
&irq_pwm,
|
||||
&irq_adc,
|
||||
&irq_dacc,
|
||||
&irq_dmac,
|
||||
&irq_uotghs,
|
||||
&irq_trng,
|
||||
&irq_emac,
|
||||
&irq_can0,
|
||||
&irq_can1,
|
||||
irq_ssc,
|
||||
irq_tc0,
|
||||
irq_tc1,
|
||||
irq_tc2,
|
||||
irq_tc3,
|
||||
irq_tc4,
|
||||
irq_tc5,
|
||||
irq_tc6,
|
||||
irq_tc7,
|
||||
irq_tc8,
|
||||
irq_pwm,
|
||||
irq_adc,
|
||||
irq_dacc,
|
||||
irq_dmac,
|
||||
irq_uotghs,
|
||||
irq_trng,
|
||||
irq_emac,
|
||||
irq_can0,
|
||||
irq_can1,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -11,20 +11,25 @@
|
|||
* Force a method to always be inlined by the compiler.
|
||||
* Do not use this for functions exceeding one or two lines.
|
||||
*/
|
||||
#define __always_inline inline __attribute__((always_inline))
|
||||
#define __always_inline inline __attribute__(( always_inline ))
|
||||
#endif /* __always_inline */
|
||||
|
||||
#ifndef __naked
|
||||
/** Function attribute for disabling register saving. */
|
||||
#define __naked __attribute__((naked))
|
||||
#define __naked __attribute__(( naked ))
|
||||
#endif
|
||||
|
||||
#ifndef __noreturn
|
||||
/** Function attribute denoting the call will never return. */
|
||||
#define __noreturn __attribute__(( noreturn ))
|
||||
#endif /* __noreturn */
|
||||
|
||||
#ifndef __weak
|
||||
/**
|
||||
* Add the `weak` attribute to a symbol.
|
||||
* This allows that identifier to be re-declared without any warnings.
|
||||
*/
|
||||
#define __weak __attribute__((__weak__))
|
||||
#define __weak __attribute__(( weak ))
|
||||
#endif /* __weak */
|
||||
|
||||
#ifndef __alias
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue