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133 lines
4.4 KiB
C
133 lines
4.4 KiB
C
/* See the end of this file for copyright, license, and warranty information. */
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#include <arch/interrupt.h>
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#include <arch/hardware.h>
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#include <arch-generic/hardware.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <string.h>
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#include <toolchain.h>
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#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
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#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
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#define SYS_BOARD_PLLAR ( \
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CKGR_PLLAR_ONE \
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| CKGR_PLLAR_MULA(0xdUL) \
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| CKGR_PLLAR_PLLACOUNT(0x3fUL) \
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| CKGR_PLLAR_DIVA(0x1UL) \
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)
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/*
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* The initial sys_core_clock on system boot would actually be 4000000 because
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* the 4 MHz RC oscillator is used by default. However, for performance
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* reasons, the system core clock is configured to use the 84 MHz PLLA clock
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* even before the memory area for global variables (like this one) is copied
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* from flash to RAM, which in turn would overwrite any updates to the clock.
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* So, since we trust the clock to be configured correctly before this global
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* variable is accessed anywhere, we initialize it to the 84 MHz clock.
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*/
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volatile uint32_t SystemCoreClock = 84000000UL;
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void sys_init(void)
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{
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/*
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* This method is basically an implementation of chapter 28.12 in the
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* Atmel SAM3X8E Datasheet, combined with the startup code from libsam.
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*/
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/* # of wait states as per hardware spec (stolen from SAM SysInit) */
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EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
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EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
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/*
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* 1. Enabling the Main Oscillator
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*/
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/* initialize main osc */
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if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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| SYS_BOARD_OSCOUNT
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| CKGR_MOR_MOSCRCEN
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| CKGR_MOR_MOSCXTEN;
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mom_are_we_there_yet(PMC->PMC_SR & PMC_SR_MOSCXTS);
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}
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/* Switch to 3-20MHz Xtal oscillator */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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| SYS_BOARD_OSCOUNT
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| CKGR_MOR_MOSCRCEN
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| CKGR_MOR_MOSCXTEN
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| CKGR_MOR_MOSCSEL;
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mom_are_we_there_yet(PMC->PMC_SR & PMC_SR_MOSCSELS);
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/*
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* 2. Checking the Main Oscillator Frequency (Optional)
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*/
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/* I repeat: **(Optional)** */
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/*
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* 3. Setting PLL and Divider
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*/
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PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
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mom_are_we_there_yet(PMC->PMC_SR & PMC_SR_MCKRDY);
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/*
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* 4. Selection of Master Clock and Processor Clock
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*/
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/* Initialize PLLA */
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PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
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mom_are_we_there_yet(PMC->PMC_SR & PMC_SR_LOCKA);
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/* Switch to MCK */
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PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
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mom_are_we_there_yet(PMC->PMC_SR & PMC_SR_MCKRDY);
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/* Switch to PLLA */
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PMC->PMC_MCKR = SYS_BOARD_MCKR;
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mom_are_we_there_yet(PMC->PMC_SR & PMC_SR_MCKRDY);
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}
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/*
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* This file is part of Ardix.
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* Copyright (c) 2020, 2021 Felix Kopp <owo@fef.moe>.
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*
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* Ardix is non-violent software: you may only use, redistribute,
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* and/or modify it under the terms of the CNPLv6+ as found in
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* the LICENSE file in the source code root directory or at
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* <https://git.pixie.town/thufie/CNPL>.
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*
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* Ardix comes with ABSOLUTELY NO WARRANTY, to the extent
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* permitted by applicable law. See the CNPLv6+ for details.
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*
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* ===========================================================================
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*
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* Parts of this file are derived from the Atmel SAM Software Package.
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* Copyright (c) 2015, Atmel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following condition is met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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