112 lines
4.1 KiB
C
112 lines
4.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/* See the end of this file for copyright, licensing, and warranty information. */
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#include <stddef.h>
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#include <stdint.h>
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#include <arch/at91sam3x8e/interrupt.h>
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#include <arch/hardware.h>
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#include <ardix/string.h>
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#include <toolchain.h>
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uint32_t sys_core_clock = 4000000UL; /* default internal 4MHz RC oscillator */
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int sys_init(void)
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{
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/*
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* This method is basically an implementation of chapter 28.12 in the
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* Atmel SAM3X8E Datasheet, combined with the startup code from libsam.
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*/
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/* # of wait states as per hardware spec (stolen from SAM SysInit) */
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REG_EEFC0_FMR = REG_EEFC_FWS_VAL(4);
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REG_EEFC1_FMR = REG_EEFC_FWS_VAL(4);
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/* disable osc write protection */
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REG_PMC_WPMR = REG_PMC_WPMR_WPKEY_VAL(REG_PMC_WPMR_WPKEY_MAGIC)
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& ~REG_PMC_WPMR_WPEN_BIT;
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/*
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* 1. Enabling the Main Oscillator
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*/
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/* initialize main osc */
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if (!(REG_CKGR_MOR & REG_CKGR_MOR_MOSCSEL_BIT)) {
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REG_CKGR_MOR = REG_CKGR_MOR_KEY_VAL(REG_CKGR_MOR_KEY_MAGIC)
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| REG_CKGR_MOR_MOSCXTST_VAL(8)
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| REG_CKGR_MOR_MOSCRCEN_BIT
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| REG_CKGR_MOR_MOSCXTEN_BIT;
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MOSCXTS_BIT);
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}
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/* switch to Xtal osc */
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REG_CKGR_MOR = REG_CKGR_MOR_KEY_VAL(REG_CKGR_MOR_KEY_MAGIC)
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| REG_CKGR_MOR_MOSCXTST_VAL(8)
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| REG_CKGR_MOR_MOSCRCEN_BIT
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| REG_CKGR_MOR_MOSCXTEN_BIT
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| REG_CKGR_MOR_MOSCSEL_BIT;
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MOSCXTS_BIT);
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REG_PMC_MCKR = (REG_PMC_MCKR & ~REG_PMC_MCKR_CSS_MASK)
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| REG_PMC_MCKR_CSS_VAL(1 /* = main clock */);
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MCKRDY_BIT);
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/*
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* 2. Checking the Main Oscillator Frequency (Optional)
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*/
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/* I repeat: **(Optional)** */
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/*
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* 3. Setting PLL and Divider
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*/
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REG_CKGR_PLLAR = REG_CKGR_PLLAR_ONE_BIT
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| REG_CKGR_PLLAR_MULA_VAL(0xD)
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| REG_CKGR_PLLAR_PLLACOUNT_VAL(0x3F /* maximum value */)
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| REG_CKGR_PLLAR_DIVA_VAL(0x1);
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_LOCKA_BIT);
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/*
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* 4. Selection of Master Clock and Processor Clock
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*/
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REG_PMC_MCKR = REG_PMC_MCKR_PRES_VAL(1 /* = as fast as it gets */)
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| REG_PMC_MCKR_CSS_VAL(1 /* = main clock */);
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MCKRDY_BIT);
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/* PMC_MCKR must not be configured within one clock cycle */
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REG_PMC_MCKR = REG_PMC_MCKR_PRES_VAL(1 /* = as fast as it gets */)
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| REG_PMC_MCKR_CSS_VAL(2 /* = PLLA clock */);
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mom_are_we_there_yet(REG_PMC_SR & REG_PMC_SR_MCKRDY_BIT);
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/* turn osc write protection on again */
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REG_PMC_WPMR |= REG_PMC_WPMR_WPEN_BIT;
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sys_core_clock = 84000000UL;
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return 0;
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}
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/*
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* Copyright (c) 2020 Felix Kopp <sandtler@sandtler.club>
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its contributors may be
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* used to endorse or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
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* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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