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@ -6,13 +6,17 @@
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* Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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* vol. 3A, chapter 9.9.1. Lines prefixed with '>' are direct quotes.
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* Annotations within those lines are enclosed in [square brackets].
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* Must be called in Real Mode, returns in Protected Mode.
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*
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* ATTENTION: This messes with the stack! Before calling this, you
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* MUST ensure that the stack pointer is aligned to 4 bytes (that is,
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* *before* the call to this subroutine pushes the return address).
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* ATTENTION: This messes with the stack! Before calling this function,
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* you MUST ensure that %sp is aligned to 4 bytes. The stack pointer
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* will be automatically translated to its linear address equivalent
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* (i.e. %esp = %ss * 0x10 + %sp), however, it DOES NOT touch %ebp.
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*
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* ATTENTION: This trashes registers %ax and %dx, as well as EFLAGS.
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* ATTENTION: You MUST call this from real mode (.code16), and any code
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* following the call MUST be for 32-bit protected mode (.code32).
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*
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* ATTENTION: This trashes %eax, %edx, eflags, and ALL segment registers.
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* Furthermore, it clears the IF flag (i.e. it disables interrupts).
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*
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> Intel 64 and IA-32 processors have slightly different requirements
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> for switching to protected mode. To ensure upwards and downwards
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@ -64,11 +68,10 @@ GLOBL real_to_prot
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> jump or call to the next instruction in the instruction stram.)
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*/
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ljmpl $0x08, $1f
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.code32
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1: .code32
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/* recompute the (now linear) stack address */
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1: xor %eax, %eax
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xor %eax, %eax
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mov %ss, %ax
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shl $4, %eax
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add %eax, %esp
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@ -87,20 +90,11 @@ GLOBL real_to_prot
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> 7. If a local descriptor table is going to be used [...]
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*
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* No.
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*/
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/*
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> 8. Execute the LTR instruction to load the task register with
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> a segment selector to the initial protected-mode task or to
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> a writable area of memory that can be used to store TSS
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> information on a task switch.
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*
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* If you insist ...
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*/
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//mov $0x28, %ax
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//ltr %ax /* offset 0x28 into GDT, 32-bit TSS */
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/*
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> 8. Execute the LTR instruction [...]
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*
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* We don't do tasks here
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*
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> 9. After entering protected mode, the segment registers continue
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> to hold the contents they had in real-address mode.
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> The JMP or CALL instruction in step 4 resets the CS register.
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@ -252,8 +246,9 @@ GLOBL prot_to_real
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out %al, $0x70
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in $0x71, %al
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jmpw *%dx
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jmp *%dx
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END prot_to_real
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.code32
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.data
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@ -265,7 +260,8 @@ END gdtr
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/*
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* This figure is based on the Intel SDM vol. 3A, fig. 5-1.
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* Reordered so that the structure matches the definition below.
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* Reordered so that the structure matches the definition below, i.e.
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* little endian byte order (bits WITHIN the bytes are big endian).
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*
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* | 0 1 | 2 3 |
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* +-------------------------------+-------------------------------+
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@ -322,23 +318,18 @@ END gdt
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.section .bss
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/* dummy IDT Register value (0 entries) */
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/* dummy IDT Register value (0 entries) */
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LOCAL prot_idtr
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.word 0
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.long 0
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END prot_idtr
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/* this is where we store the Real Mode IDT for later BIOS calls */
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/* this is where we store the Real Mode IDT for later BIOS calls */
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LOCAL real_idtr
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.word 0
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.long 0
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END real_idtr
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/* stores whether real mode sp was aligned */
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LOCAL real_sp_offset
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.word 0
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END real_sp_offset
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LOCAL real_ss
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.word 0
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END real_ss
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