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2 Commits
2bcfd294be
...
2ec426677f
| Author | SHA1 | Date |
|---|---|---|
 anna
|
2ec426677f
|
12 months ago |
|
anna
|
ce19f70440
|
12 months ago |
@ -0,0 +1,307 @@
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/*
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* Congratulations, you made it through stage0!
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* Now that we have PLENTY of space, we can proceed to doing just about the
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* same thing again with stage2. However, this time we don't have to count
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* how many bytes instructions will take up. We even adhere to a standard ABI!
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*
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* Parameters are passed through %(e)ax, %(e)dx, and then the stack.
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* Return values are passed through %(e)ax and then the stack, unless the
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* subroutine only returns a boolean in which case it sets CF=0 for true and
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* CF=1 for false. Scratch registers are %ax, %cx and %dx; the rest is
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* callee-saved.
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*
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* This file's sole responsibility is to transition from 16-bit Real Mode
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* to 32-bit Protected Mode; everything else happens in Rust.
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*/
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.extern main /* main.rs */
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.extern _bss_start /* stage1.ld */
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.extern _bss_end /* stage1.ld */
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.text
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.code16
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GLOBL _boot
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cld
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/*
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* Initialize all segment registers
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* (stage0 only guarantees a valid %cs and %ss)
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*/
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xor %ax, %ax
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %fs
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mov %ax, %gs
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/* clear .bss */
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mov $_bss_start, %di
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mov $_bss_end, %cx /* XXX we can't subtract with external symbols */
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sub %di, %cx
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shr %cx
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rep stosw
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/* stash away all the parameters stage0 pushed for us */
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pop %ax
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mov %al, boot_drive
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pop %ax
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mov %ax, (boot_lba + 4)
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pop %eax
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mov %eax, boot_lba
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mov %sp, %bp
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/* say hello */
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mov $msg_loading, %ax
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call print
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/* check the A20 line and attempt to enable it if required
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* (s/o to the engineers @ IBM, keep up the great work) */
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cli /* we don't wanna do this with interrupts */
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call a20_check
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jnc a20_enabled
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call a20_enable_bios /* try asking the BIOS */
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jc 1f
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call a20_check /* check if this acually worked */
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jnc a20_enabled
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1: call a20_enable_fast /* now try the FAST A20 method */
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call a20_check
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jnc a20_enabled
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call a20_enable /* lastly, try the old-school method */
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call a20_check
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jc err_no_a20 /* if this fails, we're screwed */
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a20_enabled:
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/* int13/00 RESET DISK SYSTEM */
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mov $0, %ah
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int $0x13
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/* make absolutely sure that %sp is aligned */
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and $0xfffc, %sp
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/* make real_to_prot return directly to rust */
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pushw $main
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jmp real_to_prot
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err_no_a20:
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mov $msg_err_no_a20, %ax
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jmp print_err_and_halt
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END _boot
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/* bool a20_check(void) */
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LOCAL a20_check
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push %si
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push %gs
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/*
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* If the A20 line is masked, memory address 0x10500 wraps around
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* to 0x00500 (in other words, 0x0000:0500 equals 0xffff:0510).
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* Check if the words at those addresses match.
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*/
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mov $0xffff, %ax
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mov %ax, %gs
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mov $_stage1_magic, %si
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mov $(_stage1_magic + 0x10), %di
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mov (%si), %ax
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cmp %gs:(%di), %ax
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jne 1f
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/*
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* Looks like the words at those addresses are the same.
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* Now make sure it's not just bad luck because something happened
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* to write our magic there. Flip the bits and see if the changes
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* are reflected in high memory.
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*/
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not %ax
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mov %ax, (%si)
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push %ax
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xor %ax, %ax
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mov $0x80, %dx
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out %al, %dx
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out %al, %dx
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out %al, %dx
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out %al, %dx
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pop %ax
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cmp %gs:(%di), %ax
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jne 1f
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stc /* return false if not enabled */
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jmp 2f
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1: clc /* return true if not not enabled */
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2: pop %gs
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pop %si
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ret
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END a20_check
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/*
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* void a20_enable(void)
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*
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* Enable the A20 gate using the old-school method introduced in the original
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* IBM PC by fucking with the keyboard controller for absolutely no reason.
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*/
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LOCAL a20_enable
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pushf
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cli
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mov $2, %al
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call a20_wait
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mov $0xad, %al
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out %al, $0x64
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mov $2, %al
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call a20_wait
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mov $0xd8, %al
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out %al, $0x64
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mov $1, %al
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call a20_wait
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in $0x60, %al
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push %ax
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mov $2, %al
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call a20_wait
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mov $0xd1, %al
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out %al, $0x64
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mov $2, %al
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call a20_wait
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pop %ax
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or $1, %ax
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out %al, $0x60
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mov $2, %al
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call a20_wait
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mov $0xae, %al
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out %al, $0x64
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mov $2, %al
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call a20_wait
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popf
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ret
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END a20_enable
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/* void a20_wait(u8 bit) */
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LOCAL a20_wait
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xchg %ax, %cx
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1: in $0x64, %al
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test %cl, %al
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jnz 1b
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ret
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END a20_wait
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/*
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* void a20_enable_fast(void)
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*
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* Enable the A20 gate using the "FAST A20" method.
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*/
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LOCAL a20_enable_fast
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in $0x92, %al
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test $2, %al
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jnz 1f
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or $2, %al
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/* make absolutely sure bit 0 is never 1 because that would
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* trigger a hot system reset, which we kinda don't want */
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and $-2, %al
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out %al, $0x92
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1: ret
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END a20_enable_fast
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/*
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* bool a20_enable_bios(void)
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*
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* Enable the A20 gate using BIOS int15/2403
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*/
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LOCAL a20_enable_bios
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pusha /* don't trust the BIOS */
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mov $0x2403, %ax
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int $0x15 /* int15/2403 QUERY A20 GATE SUPPORT */
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jc 3f /* CF = 0 on success */
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test %ah, %ah
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jnz 2f /* %ah = 0 on success */
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mov $0x2402, %ax
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int $0x15 /* int15/2402 GET A20 GATE STATUS */
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jc 3f /* CF = 0 on success */
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test %ah, %ah
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jnz 2f /* %ah = 0 on success */
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cmp $1, %al
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je 1f /* %al = 1 if enabled */
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mov $0x2401, %ax
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int $0x15 /* int15/2401 ENABLE A20 GATE */
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jc 3f /* CF = 0 on success */
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test %ah, %ah
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jnz 2f /* %ah = 0 on success */
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1: clc /* return true on success */
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jmp 3f
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2: stc /* return false on failure */
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3: popa
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ret
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END a20_enable_bios
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/* void print_err_and_halt(const char *msg) __noreturn */
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LOCAL print_err_and_halt
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call print
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mov $msg_halted, %ax
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call print
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1: cli
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hlt
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jmp 1b
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END print_err_and_halt
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/* void print(const char *msg) */
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LOCAL print
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push %bx
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push %si
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mov %ax, %si
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1: lodsb
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test %al, %al
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jz 2f
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mov $0x0e, %ah
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mov $0x0001, %bx
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int $0x10
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jmp 1b
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2: pop %si
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pop %bx
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ret
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END print
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.section .rodata
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LOCAL msg_loading, object
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.asciz "loading, please wait...\r\n"
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END msg_loading
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LOCAL msg_halted, object
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.asciz "System halted"
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END msg_halted
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LOCAL msg_err_no_a20, object
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.asciz "Error: Failed to enable the A20 line\r\n"
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END msg_err_no_a20
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.section .bss
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GLOBL boot_lba
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.quad 0
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END boot_lba
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GLOBL boot_drive
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.byte 0
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END boot_drive
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@ -0,0 +1,61 @@
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.text
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.code32
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/*
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* This has got to be one of the most cursed routines within stage1.
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* Temporarily returns to Real Mode, does a BIOS interrupt, and then
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* goes back to Protected Mode again. Furthermore, the interrupt
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* number is written ahead of time by the callee.
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*/
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GLOBL __do_bios_int
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push %ebp /* '1 v */
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mov %esp, %ebp
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pushal /* '2 v */
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mov 8(%ebp), %ebp
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mov (%ebp), %ax
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mov 2(%ebp), %cx
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mov 4(%ebp), %dx
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mov 6(%ebp), %bx
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mov 8(%ebp), %si
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mov 10(%ebp), %di
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push %ebp /* '3 v */
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push %eax /* '4 v */
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push %edx /* '5 v */
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call prot_to_real
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.code16
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pop %edx /* '5 ^ */
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pop %eax /* '4 ^ */
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/* call that polymorphism! */
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.byte 0xcd /* opcode for `int imm8` */
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GLOBL __bios_int_number, object
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.byte 0x18 /* this is the imm8 */
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push %eax /* '4 v */
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push %edx /* '5 v */
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pushfl /* '6 v */
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call real_to_prot
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.code32
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popfl /* '6 ^ */
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pop %edx /* '5 ^ */
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pop %eax /* '4 ^ */
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pop %ebp /* '3 ^ */
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mov %ax, (%ebp)
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mov %cx, 2(%ebp)
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mov %dx, 4(%ebp)
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mov %bx, 6(%ebp)
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mov %si, 8(%ebp)
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mov %di, 10(%ebp)
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mov %al, 12(%ebp)
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popal /* '2 ^ */
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setc %al
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movzbl %al, %eax
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pop %ebx /* '1 ^ */
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ret
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END __do_bios_int
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@ -0,0 +1,344 @@
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.text
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/*
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* Transition from Real Mode to Protected Mode as outlined in the
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* Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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* vol. 3A, chapter 9.9.1. Lines prefixed with '>' are direct quotes.
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* Annotations within those lines are enclosed in [square brackets].
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* Must be called in Real Mode, returns in Protected Mode.
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*
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* ATTENTION: This messes with the stack! Before calling this, you
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* MUST ensure that the stack pointer is aligned to 4 bytes (that is,
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* *before* the call to this subroutine pushes the return address).
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*
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* ATTENTION: This trashes registers %ax and %dx, as well as EFLAGS.
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*
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> Intel 64 and IA-32 processors have slightly different requirements
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> for switching to protected mode. To ensure upwards and downwards
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> code compatibility with Intel 64 and IA-32 processors, we recommend
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> that you follow these steps:
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*/
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GLOBL real_to_prot
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.code16
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/* okay we have to be a little careful with this one */
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/*
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> 1. Disable interrupts. A CLI instruction disables maskable hardware
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> interrupts. NMI interrupts can be disabled with external circuitry.
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*
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* So we mask the Non-Maskable Interrupt. Truly an x86 moment.
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*/
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cli
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in $0x70, %al
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or $0x80, %al
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out %al, $0x70
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in $0x71, %al
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/* Grab the return address and store the old %ss */
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xor %edx, %edx
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pop %dx /* %dx = return address */
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mov %ss, %ax
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mov %ax, real_ss
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||||
/*
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||||
> 2. Execute the LGDT instruction to load the GDTR register
|
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> with the base address of the GDT.
|
||||
*/
|
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lgdt gdtr
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|
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/*
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||||
> 3. Execute a MOV CR0 instruction that sets the PE flag
|
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> (and optionally the PG flag) in control register CR0.
|
||||
*
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* We don't use paging but we DO want to set the Protection Enable bit.
|
||||
*/
|
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mov %cr0, %eax
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or $1, %al
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mov %eax, %cr0
|
||||
|
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/*
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||||
> 4. Immediately following the MOV CR0 instruction, execute a far
|
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> JMP or far CALL instruction. (This operation is typically a far
|
||||
> jump or call to the next instruction in the instruction stram.)
|
||||
*/
|
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ljmpl $0x08, $1f
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|
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.code32
|
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|
||||
/* recompute the (now linear) stack address */
|
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1: xor %eax, %eax
|
||||
mov %ss, %ax
|
||||
shl $4, %eax
|
||||
add %eax, %esp
|
||||
|
||||
/*
|
||||
> 5. The JMP or CALL instruction immediately after the MOV CR0
|
||||
> instruction changes the flow of execution and serializes
|
||||
> the processor.
|
||||
*
|
||||
* Ok.
|
||||
*
|
||||
> 6. If paging is enabled [...]
|
||||
*
|
||||
* It is not.
|
||||
*
|
||||
> 7. If a local descriptor table is going to be used [...]
|
||||
*
|
||||
* No.
|
||||
*/
|
||||
|
||||
/*
|
||||
> 8. Execute the LTR instruction to load the task register with
|
||||
> a segment selector to the initial protected-mode task or to
|
||||
> a writable area of memory that can be used to store TSS
|
||||
> information on a task switch.
|
||||
*
|
||||
* If you insist ...
|
||||
*/
|
||||
//mov $0x28, %ax
|
||||
//ltr %ax /* offset 0x28 into GDT, 32-bit TSS */
|
||||
|
||||
/*
|
||||
> 9. After entering protected mode, the segment registers continue
|
||||
> to hold the contents they had in real-address mode.
|
||||
> The JMP or CALL instruction in step 4 resets the CS register.
|
||||
> Perform one of the folowing operations to update the contents
|
||||
> of the remaining segment registers.
|
||||
>
|
||||
> - Reload segment registers DS, SS, ES, FS, and GS.
|
||||
> If the ES, FS, and/or GS registers are not going to be used,
|
||||
> load them with a null selector.
|
||||
> - [...]
|
||||
*/
|
||||
|
||||
mov $0x10, %ax
|
||||
mov %ax, %ds
|
||||
mov %ax, %ss
|
||||
mov %ax, %es
|
||||
xor %eax, %eax
|
||||
mov %ax, %fs
|
||||
mov %ax, %gs
|
||||
|
||||
/*
|
||||
> 10. Execute the LIDT instruction to load the IDTR register
|
||||
> with the address and limit of the protected-mode IDT.
|
||||
*
|
||||
* Ok but before doing that, we need to stash away the old IDTR
|
||||
* so we can return to Real Mode and make BIOS calls later.
|
||||
*/
|
||||
sidt real_idtr
|
||||
lidt prot_idtr
|
||||
|
||||
/*
|
||||
> 11. Execute the STI instruction to enable maskable hardware
|
||||
> interrupts and perform the necessary hardware operation
|
||||
> to enable NMI interrupts.
|
||||
*
|
||||
* We don't really do interrupts in stage1, but we can enable NMI.
|
||||
*/
|
||||
in $0x70, %al
|
||||
and $0x7f, %al
|
||||
out %al, $0x70
|
||||
in $0x71, %al
|
||||
|
||||
jmp *%edx
|
||||
END real_to_prot
|
||||
|
||||
/*
|
||||
* Do the exact opposite of real_to_prot, i.e. transition from
|
||||
* Protected Mode to Real Mode (in order to make BIOS calls).
|
||||
* Again, this is quoted from the Intel SDM vol. 3A, but this time
|
||||
* from chapter 9.9.2.
|
||||
*
|
||||
* ATTENTION: This messes with the stack! Every call to prot_to_real
|
||||
* MUST be followed by a call to real_to_prot, and that call MUST
|
||||
* happen with the same stack pointer value.
|
||||
*
|
||||
> The processor switches from protected mode back to real-address
|
||||
> mode if software clears the PE bit in the CR0 register with a
|
||||
> MOV CR0 instruction. A procedure that re-enters real-address mode
|
||||
> should perform the following steps:
|
||||
*/
|
||||
GLOBL prot_to_real
|
||||
.code32
|
||||
|
||||
/*
|
||||
> 1. Disable interrupts. [...]
|
||||
*/
|
||||
cli
|
||||
in $0x70, %al
|
||||
or $0x80, %al
|
||||
out %al, $0x70
|
||||
in $0x71, %al
|
||||
|
||||
/* fuck with the stack */
|
||||
pop %edx /* %edx = return address */
|
||||
xor %eax, %eax
|
||||
mov real_ss, %ax
|
||||
shl $4, %eax
|
||||
sub %eax, %esp
|
||||
|
||||
/*
|
||||
> 2. If paging is enabled, [...]
|
||||
*
|
||||
* It is not.
|
||||
*
|
||||
> 3. Transfer program control to a readable segment that has a limit
|
||||
> of 64 KBytes (FFFFH). This operation loads the CS register with
|
||||
> the segment limit required in real-address mode.
|
||||
*/
|
||||
ljmp $0x18, $1f
|
||||
1: .code16
|
||||
|
||||
/*
|
||||
> 4. Load segment registers SS, DS, ES, FS, and GS with a selector
|
||||
> for a descriptor containing the following values, which are
|
||||
> appropriate for real-address mode:
|
||||
>
|
||||
> - [...]
|
||||
*
|
||||
* See offset 0x20 in _gdt.
|
||||
*/
|
||||
mov $0x20, %ax
|
||||
mov %ax, %ds
|
||||
mov %ax, %ss
|
||||
mov %ax, %es
|
||||
mov %ax, %fs
|
||||
mov %ax, %gs
|
||||
|
||||
/*
|
||||
> 5. Execute the LIDT instruction to point to a real-address mode interrupt
|
||||
> table that is within the 1-MByte real-address mode address range.
|
||||
*/
|
||||
sidt prot_idtr
|
||||
lidt real_idtr
|
||||
|
||||
/*
|
||||
> 6. Clear the PE flag in the CR0 register to switch to real-address mode.
|
||||
*/
|
||||
mov %cr0, %eax
|
||||
and $0xfe, %al
|
||||
mov %eax, %cr0
|
||||
|
||||
/*
|
||||
> 7. Execute a far JMP instruction to jump to a real-address mode
|
||||
> program. This operation flushes the instruction queue and loads
|
||||
> the appropriate base-address value in the CS register.
|
||||
*/
|
||||
ljmp $0x00, $1f
|
||||
|
||||
/*
|
||||
> 8. Load the SS, DS, ES, FS, and GS registers as needed by the
|
||||
> real-address mode code. If any of the registers are not going
|
||||
> to be used in real-address mode, write 0s to them.
|
||||
*/
|
||||
1: mov real_ss, %ax
|
||||
mov %ax, %ss
|
||||
xor %ax, %ax
|
||||
mov %ax, %ds
|
||||
mov %ax, %es
|
||||
mov %ax, %fs
|
||||
mov %ax, %gs
|
||||
|
||||
/*
|
||||
> 9. Execute the STI instruction to enable maskable hardware
|
||||
> interrupts and perform the necessary hardware operation
|
||||
> to enable NMI interrupts.
|
||||
*/
|
||||
in $0x70, %al
|
||||
and $0x7f, %al
|
||||
out %al, $0x70
|
||||
in $0x71, %al
|
||||
|
||||
jmpw *%dx
|
||||
END prot_to_real
|
||||
|
||||
.data
|
||||
|
||||
.align 32
|
||||
LOCAL gdtr
|
||||
.word gdt_end - gdt - 1
|
||||
.long gdt
|
||||
END gdtr
|
||||
|
||||
/*
|
||||
* This figure is based on the Intel SDM vol. 3A, fig. 5-1.
|
||||
* Reordered so that the structure matches the definition below.
|
||||
*
|
||||
* | 0 1 | 2 3 |
|
||||
* +-------------------------------+-------------------------------+
|
||||
* | Segment Limit | Base Address |
|
||||
* +0 | | |
|
||||
* | 00:15 | 00:15 |
|
||||
* +---------------+-+---+-+-+-+-+-+-+-+-+-+-------+---------------+
|
||||
* | Base | | D |1|0|E|W|A| |B| |A| Limit | Base | < data
|
||||
* +4 | |P| P | Type |G|/|0|V| | |
|
||||
* | 16:23 | | L |1|1|C|R|A| |D| |L| 16:19 | 24:31 | < code
|
||||
* +---------------+-+---+-+-+-+-+-+-+-+-+-+-------+---------------+
|
||||
* | 4 | 5 | 6 | 7 |
|
||||
*
|
||||
* A Accessed E Expansion Direction (0=up)
|
||||
* AVL Available to System Programmers G Granularity (0=1B, 1=4K)
|
||||
* B Big (32-bit code) R Readable
|
||||
* C Conforming W Writable
|
||||
* D Default P Present
|
||||
* DPL Descriptor Privilege Level
|
||||
*
|
||||
* The GDT is a Very Normal data structure.
|
||||
*/
|
||||
.align 32
|
||||
LOCAL gdt
|
||||
/* 0x00 null descriptor */
|
||||
.word 0x0000, 0x0000
|
||||
.byte 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/* 0x08 32-bit code */
|
||||
/* | Limit = 0xfffff | Base = 0x00000000 | */
|
||||
.word 0xffff, 0x0000
|
||||
/* | |P 0 0 1|1 R |G D 0 /| 0xf | | */
|
||||
.byte 0x00, 0x9a, 0xcf, 0x00
|
||||
|
||||
/* 0x10 32-bit data */
|
||||
/* | Limit = 0xfffff | Base = 0x00000000 | */
|
||||
.word 0xffff, 0x0000
|
||||
/* | |P 0 0 1|0 W |G B 0 /| 0xf | | */
|
||||
.byte 0x00, 0x92, 0xcf, 0x00
|
||||
|
||||
/* 0x18 16-bit code */
|
||||
/* | Limit = 0x0ffff | Base = 0x00000000 | */
|
||||
.word 0xffff, 0x0000
|
||||
/* | |P 0 0 1|1 C R | 0 /| 0x0 | | */
|
||||
.byte 0x00, 0x9e, 0x00, 0x00
|
||||
|
||||
/* 0x20 16-bit data */
|
||||
/* | Limit = 0x0ffff | Base = 0x00000000 | */
|
||||
.word 0xffff, 0x0000
|
||||
/* | |P 0 0 1|0 W | 0 /| 0x0 | | */
|
||||
.byte 0x00, 0x92, 0x00, 0x00
|
||||
gdt_end:
|
||||
END gdt
|
||||
|
||||
.section .bss
|
||||
|
||||
/* dummy IDT Register value (0 entries) */
|
||||
LOCAL prot_idtr
|
||||
.word 0
|
||||
.long 0
|
||||
END prot_idtr
|
||||
|
||||
/* this is where we store the Real Mode IDT for later BIOS calls */
|
||||
LOCAL real_idtr
|
||||
.word 0
|
||||
.long 0
|
||||
END real_idtr
|
||||
|
||||
/* stores whether real mode sp was aligned */
|
||||
LOCAL real_sp_offset
|
||||
.word 0
|
||||
END real_sp_offset
|
||||
|
||||
LOCAL real_ss
|
||||
.word 0
|
||||
END real_ss
|
||||
Loading…
Reference in New Issue