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Added some notes on PCI chipsets and their quirks.

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Submitted by:	jhk@freebsd.org for rgrimes@freebsd.org
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John Fieber 1995-08-25 22:14:30 +00:00
parent a965e8a2b7
commit 1adff3888d
Notes: svn2git 2020-12-08 03:00:23 +00:00 
svn path=/head/; revision=59
2 changed files with 59 additions and 5 deletions
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handbook/authors.sgml
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<!-- $Id: authors.sgml,v 1.5 1995-07-29 13:08:00 jfieber Exp $ -->
<!-- $Id: authors.sgml,v 1.6 1995-08-25 22:14:28 jfieber Exp $ -->
<!-- The FreeBSD Documentation Project -->
<!--
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<!ENTITY a.nik "Nik Clayton <tt>&lt;nik@blueberry.co.uk&gt;</tt>">
<!ENTITY a.phk "Poul-Henning Kamp <tt>&lt;phk@FreeBSD.org&gt;</tt>">
<!ENTITY a.paul "Paul Richards <tt>&lt;paul@FreeBSD.org&gt;</tt>">
<!ENTITY a.rgrimes "Rodney Grimes <tt>&lt;rgrimes@FreeBSD.org&gt;</tt>">
<!ENTITY a.wilko "Wilko Bulte <tt>&lt;wilko@yedi.iaf.nl&gt;</tt>">

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handbook/hw.sgml
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<!-- $Id: hw.sgml,v 1.2 1995-06-20 16:29:54 jfieber Exp $ -->
<!-- $Id: hw.sgml,v 1.3 1995-08-25 22:14:30 jfieber Exp $ -->
<!-- The FreeBSD Documentation Project -->
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<!DOCTYPE linuxdoc PUBLIC "-//FreeBSD//DTD linuxdoc//EN">
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<chapt><heading>PC Hardware compatibility<label id="hw"></heading>
<p>Issues of hardware compatibility are among the most
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FreeBSD you are using and include as many details of your
hardware as possible.
<sect><heading>* Core/Processing<label id="hw:core"></heading>
<sect><heading>Core/Processing<label id="hw:core"></heading>
<sect1><heading>* Motherboards</heading>
<sect1><heading>Motherboards, busses, and chipsets</heading>
<sect2><heading>* ISA</heading>
<sect2><heading>* EISA</heading>
<sect2><heading>* VLB</heading>
<sect2><heading>* PCI</heading>
<sect2><heading>PCI</heading>
<p><em>Contributed by &a.rgrimes;.<newline>25 April 1995.</em></p>
<p>Of the Intel PCI chip sets the following is a list
of brokenness from worst to best and a short
description of brokenness.</p>
<p><descrip>
<tag>Mercury:</tag> Cache coherency problems,
especially if there are ISA bus masters behind
the ISA to PCI bridge chip. Hardware flaw, only
known work around is to turn the cache
off.
<tag>Saturn-I <em>(ie, 82424ZX at rev 0, 1 or
2)</em>:</tag> write back cache coherency
problems. Hardware flaw, only known work around
is to set the external cache to write-through
mode. Upgrade to Saturn-II.
<tag>Saturn-II <em>(ie, 82424ZX at rev 3 or
4)</em>:</tag> Works fine, but many MB
manufactures leave out the external dirty bit
SRAM needed for write back operation. Work
arounds are either run it in write through mode,
or get the dirty bit SRAM installed. (I have
these for the ASUS PCI/I-486SP3G rev 1.6 and
later boards).
<tag>Neptune:</tag> Can not run more than 2 bus
master devices. Admitted Intel design flaw.
Workarounds include don't run more than 2 bus
masters, special hardware design to replace the
PCI bus arbiter (appears on Intel Altair board
and several other Intel server group MB's). And
of course Intel's official answer, move to the
Triton chip set, we ``fixed it there''.
<tag>Triton:</tag> No known cache coherency or bus
master problems, chip set does not implement
parity checking. Workaround for parity issue.
Wait for Triton-II.
<tag>Triton-II:</tag> Unknown, not yet shipping.
</descrip>
</p>
<sect1><heading>* CPUs/FPUs</heading>
<sect1><heading>* Memory</heading>
<sect1><heading>* BIOS</heading>