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- add SandyBridge status reports

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Submitted by:	kib
This commit is contained in:
Daniel Gerzo 2012-01-25 13:50:42 +00:00
parent 981cda05c5
commit 9814ea27d0
Notes: svn2git 2020-12-08 03:00:23 +00:00 
svn path=/www/; revision=38307
1 changed files with 47 additions and 2 deletions
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49
en/news/status/report-2011-10-2011-12.xml
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="ISO-8859-1" ?>
<!DOCTYPE report PUBLIC "-//FreeBSD//DTD FreeBSD XML Database for Status
Report//EN" "http://www.FreeBSD.org/XML/www/share/sgml/statusreport.dtd">
<!-- $FreeBSD: www/en/news/status/report-2011-10-2011-12.xml,v 1.3 2012/01/22 17:14:42 danger Exp $ -->
<!-- $FreeBSD: www/en/news/status/report-2011-10-2011-12.xml,v 1.4 2012/01/25 13:22:42 uqs Exp $ -->
<report>
<date>
<month>October-December</month>
@ -19,7 +19,7 @@ Report//EN" "http://www.FreeBSD.org/XML/www/share/sgml/statusreport.dtd">
the beginning of January 2012.</p>
<p>Thanks to all the reporters for the excellent work! This report
contains 29 entries and we hope you enjoy reading it.</p>
contains 30 entries and we hope you enjoy reading it.</p>
<p>Please note that the deadline for submissions covering the period
between January and March 2012 is April 15th, 2012.</p>
@ -1762,4 +1762,49 @@ Report//EN" "http://www.FreeBSD.org/XML/www/share/sgml/statusreport.dtd">
<task>Test more hardware?</task>
</help>
</project>
<project cat='arch'>
<title>Improving support for new features in Intel SandyBridge CPUs</title>
<contact>
<person>
<name>
<given>Konstantin</given>
<common>Belousov</common>
</name>
<email>kib@FreeBSD.org</email>
</person>
</contact>
<body>
<p>Support for new features in the Intel SandyBridge CPUs is
progressing.</p>
<p>The patch to query and allow extended FPU states was committed,
which enabled the YMM registers and AVX instruction set on the
capable processors. Todo items include get wider testing of the
change before planned merge to stable/9 in a month, and start
using XSAVEOPT instruction to optimize context switch times.</p>
<p>Patch to enable and use per-process TLB was developed. Latest
version is available at <a
href="http://people.freebsd.org/~kib/misc/pcid.2.patch">
http://people.freebsd.org/~kib/misc/pcid.2.patch</a>. The facility,
referred in the documentation as PCID, allows to avoid TLB flush
on context switches by applying PID tag to each non-global TLB
entry. On SandyBridge, measurements did not prove any difference
between context switch latencies on patched and stock kernels.</p>
<p>Forthcoming IvyBridge CPUs promised to provide optimizations in
the form of INVPCID instructions that allow to optimize TLB
shootdown handlers. Patch above uses the instruction on the
capable CPU. Todo items are to get access to IvyBridge and do the
benchmarks.</p>
<p>Future work might provde SEP support, use hardware random
generator from IvyBridge for random(4), considering using faster
instructions to access fs% and gs% bases, and use improved AES-NI
instruction set for aesni(4).</p>
</body>
</project>
</report>