x86: refactor traps, add register dump support
parent
3e43ec5491
commit
d69fd0d2aa
GPG Key ID:
EC22E476DC2D3D84
@ -1,175 +0,0 @@
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/* See the end of this file for copyright and license terms. */
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#include <arch/interrupt.h>
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#include <asm/common.h>
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.text
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/*
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* low level entry points, this is what gets put into the IDT
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*/
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ASM_ENTRY(_x86_isr_divide_error)
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cld
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call x86_isr_divide_error
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iret
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ASM_END(_x86_isr_divide_error)
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ASM_ENTRY(_x86_isr_debug_exception)
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cld
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call x86_isr_debug_exception
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iret
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ASM_END(_x86_isr_debug_exception)
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ASM_ENTRY(_x86_isr_nmi)
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cld
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call x86_isr_nmi
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iret
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ASM_END(_x86_isr_nmi)
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ASM_ENTRY(_x86_isr_breakpoint)
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cld
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call x86_isr_breakpoint
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iret
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ASM_END(_x86_isr_breakpoint)
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ASM_ENTRY(_x86_isr_overflow)
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cld
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call x86_isr_overflow
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iret
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ASM_END(_x86_isr_overflow)
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ASM_ENTRY(_x86_isr_bound_range_exceeded)
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cld
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call x86_isr_bound_range_exceeded
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iret
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ASM_END(_x86_isr_bound_range_exceeded)
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ASM_ENTRY(_x86_isr_invalid_opcode)
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cld
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call x86_isr_invalid_opcode
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iret
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ASM_END(_x86_isr_invalid_opcode)
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ASM_ENTRY(_x86_isr_device_not_available)
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cld
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call x86_isr_device_not_available
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iret
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ASM_END(_x86_isr_device_not_available)
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ASM_ENTRY(_x86_isr_double_fault)
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cld
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call x86_isr_double_fault
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add $4, %esp
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iret
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ASM_END(_x86_isr_double_fault)
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ASM_ENTRY(_x86_isr_invalid_tss)
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cld
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call x86_isr_invalid_tss
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add $4, %esp
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iret
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ASM_END(_x86_isr_invalid_tss)
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ASM_ENTRY(_x86_isr_segment_not_present)
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cld
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call x86_isr_segment_not_present
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add $4, %esp
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iret
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ASM_END(_x86_isr_segment_not_present)
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ASM_ENTRY(_x86_isr_stack_segment_fault)
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cld
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call x86_isr_stack_segment_fault
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add $4, %esp
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iret
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ASM_END(_x86_isr_stack_segment_fault)
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ASM_ENTRY(_x86_isr_general_protection)
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cld
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call x86_isr_general_protection
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add $4, %esp
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iret
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ASM_END(_x86_isr_general_protection)
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ASM_ENTRY(_x86_isr_page_fault)
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cld
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call x86_isr_page_fault
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add $4, %esp
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iret
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ASM_END(_x86_isr_page_fault)
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ASM_ENTRY(_x86_isr_x87_fpu_error)
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cld
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call x86_isr_x87_fpu_error
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iret
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ASM_END(_x86_isr_fpu_error)
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ASM_ENTRY(_x86_isr_alignment_check)
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cld
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call x86_isr_alignment_check
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add $4, %esp
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iret
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ASM_END(_x86_isr_alignment_check)
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ASM_ENTRY(_x86_isr_machine_check)
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cld
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call x86_isr_machine_check
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iret
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ASM_END(_x86_isr_machine_check)
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ASM_ENTRY(_x86_isr_simd_floating_point_exception)
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cld
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call x86_isr_simd_floating_point_exception
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iret
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ASM_END(_x86_isr_simd_floating_point_exception)
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ASM_ENTRY(_x86_isr_virtualization_exception)
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cld
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call x86_isr_virtualization_exception
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iret
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ASM_END(_x86_isr_virtualization_exception)
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ASM_ENTRY(_x86_isr_control_protection_exception)
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cld
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call x86_isr_control_protection_exception
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add $4, %esp
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iret
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ASM_END(_x86_isr_control_protection_exception)
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/* trap.c */
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.extern x86_isr_divide_error
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.extern x86_isr_debug_exception
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.extern x86_isr_nmi
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.extern x86_isr_breakpoint
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.extern x86_isr_overflow
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.extern x86_isr_bound_range_exceeded
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.extern x86_isr_invalid_opcode
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.extern x86_isr_device_not_available
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.extern x86_isr_double_fault
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.extern x86_isr_invalid_tss
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.extern x86_isr_segment_not_present
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.extern x86_isr_stack_segment_fault
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.extern x86_isr_general_protection
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.extern x86_isr_page_fault
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.extern x86_isr_x87_fpu_error
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.extern x86_isr_alignment_check
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.extern x86_isr_machine_check
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.extern x86_isr_simd_floating_point_exception
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.extern x86_isr_virtualization_exception
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.extern x86_isr_control_protection_exception
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/*
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* This file is part of GayBSD.
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* Copyright (c) 2021 fef <owo@fef.moe>.
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*
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* GayBSD is nonviolent software: you may only use, redistribute, and/or
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* modify it under the terms of the Cooperative Nonviolent Public License
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* (CNPL) as found in the LICENSE file in the source code root directory
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* or at <https://git.pixie.town/thufie/npl-builder>; either version 7
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* of the license, or (at your option) any later version.
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*
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* GayBSD comes with ABSOLUTELY NO WARRANTY, to the extent
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* permitted by applicable law. See the CNPL for details.
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*/
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@ -0,0 +1,102 @@
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/* See the end of this file for copyright and license terms. */
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#include <arch/interrupt.h>
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#include <asm/common.h>
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.text
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/*
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* Low level trap entry points, this is what gets put into the IDT.
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*
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* Hardware automatically pushes EFLAGS, CS, EIP, and (optionally) an error
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* code to the stack. The rest is pushed by software using the pushal
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* instruction. I wanted to use the same context save struct for both kinds
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* of exceptions (the ones that push an error code and the ones that don't),
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* so the pointer to the hardware context save is also pushed to the stack and
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* included in struct x86_trap_frame.
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*/
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.macro gen_isr_noerror name
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.extern x86_isr_\name
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ASM_ENTRY(_x86_isr_\name )
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cld
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pushal
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mov %esp, %eax
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add $32, %eax
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push %eax
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call x86_isr_\name
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add $4, %esp
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popal
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iretl
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ASM_END(_x86_isr_\name )
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.endm
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/*
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* So, instead of just adding a dedicated register for exception status, the
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* Intel people apparently thought it was better to have the CPU push an error
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* code to the stack. This is technically not too bad of an idea because the
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* x86 ABI says all parameters are passed through the stack, so you could write
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* exception handlers in C! Too bad the CPU (1) doesn't save scratch registers
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* eax, ecx and edx automatically, (2) only some of the exceptions push this
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* error code?? and (3) you have to pop the error code manually??????
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*/
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.macro gen_isr_error name
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.extern x86_isr_\name
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ASM_ENTRY(_x86_isr_\name )
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cld
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pushal
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mov %esp, %eax
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add $36, %eax
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push %eax /* struct x86_trap_frame::hw_frame */
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/*
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* pushal pushes 8 registers = 32 bytes to the stack, plus 4 bytes
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* for the pointer to struct x86_hw_frame, so the error code pushed
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* by hardware is 36 bytes into %esp now
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*/
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mov 36(%esp), %ebx
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mov %esp, %eax
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push %ebx
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push %eax
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call x86_isr_\name /* x86_isr_<name>(%esp, error_code); */
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add $8, %esp
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popal
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add $4, %esp /* "pop" the hardware error code from the stack */
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iretl
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ASM_END(_x86_isr_\name )
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.endm
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gen_isr_noerror divide_error
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gen_isr_noerror debug_exception
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gen_isr_noerror nmi
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gen_isr_noerror breakpoint
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gen_isr_noerror overflow
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gen_isr_noerror bound_range_exceeded
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gen_isr_noerror invalid_opcode
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gen_isr_noerror device_not_available
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gen_isr_error double_fault
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gen_isr_error invalid_tss
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gen_isr_error segment_not_present
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gen_isr_error stack_segment_fault
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gen_isr_error general_protection
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gen_isr_error page_fault
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gen_isr_noerror x87_fpu_error
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gen_isr_error alignment_check
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gen_isr_noerror machine_check
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gen_isr_noerror simd_floating_point_exception
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gen_isr_noerror virtualization_exception
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gen_isr_error control_protection_exception
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/*
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* This file is part of GayBSD.
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* Copyright (c) 2021 fef <owo@fef.moe>.
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*
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* GayBSD is nonviolent software: you may only use, redistribute, and/or
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* modify it under the terms of the Cooperative Nonviolent Public License
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* (CNPL) as found in the LICENSE file in the source code root directory
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* or at <https://git.pixie.town/thufie/npl-builder>; either version 7
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* of the license, or (at your option) any later version.
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*
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* GayBSD comes with ABSOLUTELY NO WARRANTY, to the extent
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* permitted by applicable law. See the CNPL for details.
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*/
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