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@ -9,18 +9,29 @@
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#include <arch/at91sam3x8e/interrupt.h>
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#include <arch/serial.h>
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#include <stddef.h>
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struct serial_interface arch_serial_default_interface = {
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.tx = NULL,
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.rx = NULL,
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.id = 0,
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.baud = 0,
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};
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struct serial_interface *serial_default_interface = &arch_serial_default_interface;
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int arch_serial_init(struct serial_interface *interface)
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{
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if (interface->baud <= 0 || interface->id != 0)
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return -1;
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/* enable peripheral clock for UART (which has peripheral id 8) */
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REG_PMC_PCER0 = REG_PMC_PCER0_PID(8);
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REG_PMC_PCER0 |= REG_PMC_PCER0_PID(8);
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/* UART is multiplexed with PIOA, so we need to enable that controller first */
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REG_PIO_WPMR(PIOA) = REG_PIO_WPMR_WPEN_VAL(0); /* turn write protection off */
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REG_PIO_PER(PIOA) = (1 << 8) | (1 << 9);
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REG_PIO_WPMR(PIOA) = REG_PIO_WPMR_WPEN_VAL(1); /* turn write protection back on */
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/* ensure the PIO controller is turned off on the serial pins */
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REG_PIO_PDR(PIOA) = (1 << 8) | (1 << 9);
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/* turn off PDC channel (we are manually writing byte-by-byte here) */
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REG_UART_PDC_PTCR = REG_UART_PDC_PTCR_RXTDIS_MASK | REG_UART_PDC_PTCR_TXTDIS_MASK;
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/* reset & disable rx and tx */
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REG_UART_CR = REG_UART_CR_RXDIS_MASK | REG_UART_CR_RSTRX_MASK
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@ -30,15 +41,16 @@ int arch_serial_init(struct serial_interface *interface)
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REG_UART_MR = REG_UART_MR_PAR_NO | REG_UART_MR_CHMODE_NORMAL;
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/* From Atmel Datasheet: baud rate = MCK / (REG_UART_BRGR * 16) */
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REG_UART_BRGR = (uint16_t)((sys_core_clock / (uint32_t)interface->baud) >> 4);
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REG_UART_BRGR = (uint16_t)(( sys_core_clock / (uint32_t)interface->baud ) >> 4);
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/* choose the events we want an interrupt on */
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REG_UART_IDR = 0xFFFFFFFF; /* make sure all interrupts are disabled first */
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REG_UART_IER = REG_UART_IER_RXRDY_MASK | REG_UART_IER_OVRE_MASK | REG_UART_IER_FRAME_MASK;
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/* TXRDY is not selected because the output buffer is initially empty anyway */
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REG_UART_IER = REG_UART_IER_RXRDY_MASK | REG_UART_IER_OVRE_MASK | REG_UART_IER_FRAME_MASK | REG_UART_IER_TXRDY_MASK;
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arch_irq_enable(IRQNO_UART);
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/* enable transmitter and receiver */
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/* enable receiver and transmitter */
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REG_UART_CR = REG_UART_CR_RXEN_MASK | REG_UART_CR_TXEN_MASK;
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return 0;
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@ -49,43 +61,55 @@ void arch_serial_exit(struct serial_interface *interface)
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if (interface->id != 0)
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return;
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/* disable receiver and transmitter */
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REG_UART_CR = REG_UART_CR_RXDIS_MASK | REG_UART_CR_TXDIS_MASK;
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arch_irq_disable(IRQNO_UART);
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/* disable I/O line */
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REG_PIO_WPMR(PIOA) = REG_PIO_WPMR_WPEN_VAL(1);
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REG_PIO_PER(PIOA) = (1 << 8) | (1 << 9);
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REG_PIO_WPMR(PIOA) = REG_PIO_WPMR_WPEN_VAL(0);
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/* disable peripheral clock for UART */
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/* disable peripheral clock for UART (PID is taken from Atmel Datasheet, Section 9.1 */
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REG_PMC_PCDR0 = REG_PMC_PCDR0_PID(8);
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}
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int arch_serial_op_begin(struct serial_interface *interface)
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{
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/* TODO */
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return -1;
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interface->id = -1;
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}
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ssize_t arch_serial_op_read(struct serial_interface *interface)
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void arch_serial_notify(struct serial_interface *interface)
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{
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/* TODO */
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return 0;
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/* unmask the TXRDY interrupt */
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REG_UART_IER = REG_UART_IER_TXRDY_MASK;
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}
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ssize_t arch_serial_op_write(struct serial_interface *interface)
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void irq_uart(void)
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{
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/* TODO */
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return 0;
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uint8_t tmp;
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size_t len;
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uint32_t state = REG_UART_SR;
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/* RX has received a byte, store it into the ring buffer */
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if (state & REG_UART_SR_RXRDY_MASK) {
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tmp = REG_UART_RHR;
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ringbuf_write(serial_default_interface->rx, &tmp, sizeof(tmp));
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}
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/* TX is ready to transmit the next byte */
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if (state & REG_UART_SR_TXRDY_MASK) {
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len = ringbuf_read(&tmp, serial_default_interface->tx, sizeof(tmp));
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if (len) {
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/* there is data in the queue, so write it to TX holding register */
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REG_UART_THR = tmp;
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} else {
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/* TX queue is empty, mask the TXRDY event */
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REG_UART_IDR = REG_UART_IDR_TXRDY_MASK;
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}
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}
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/* check for error conditions */
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if ((state & REG_UART_SR_OVRE_MASK) || (state & REG_UART_SR_FRAME_MASK)) {
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/* TODO: write some proper error handling routines ffs */
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REG_UART_CR = REG_UART_CR_RSTSTA_MASK;
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}
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}
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struct serial_operations arch_serial_operations = {
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.begin = &arch_serial_op_begin,
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.read = &arch_serial_op_read,
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.write = &arch_serial_op_write,
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};
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/*
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* Copyright (c) 2020 Felix Kopp <sandtler@sandtler.club>
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*
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