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The 'Protection Enabled' bit is part of CR0 not CR1 register.

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Submitted by:	Petros Barbagiannis (petros.barbagiannis at gmail)
This commit is contained in:
Giorgos Keramidas 2012-01-09 13:43:07 +00:00
parent cb24cd6bd0
commit 29eaa0176d
Notes: svn2git 2020-12-08 03:00:23 +00:00 
svn path=/head/; revision=38161
1 changed files with 2 additions and 2 deletions
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en_US.ISO8859-1/books/arch-handbook/boot/chapter.sgml
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@ -136,8 +136,8 @@ Timecounter "i8254" frequency 1193182 Hz</screen></para></entry>
after a power on is well defined: it is a 32-bit value of
0xfffffff0. The instruction pointer register points to code to
be executed by the processor. One of the registers is the
<literal>cr1</literal> 32-bit control register, and its value
just after the reboot is 0. One of the cr1's bits, the bit PE
<literal>cr0</literal> 32-bit control register, and its value
just after the reboot is 0. One of the cr0's bits, the bit PE
(Protected Enabled) indicates whether the processor is running
in protected or real mode. Since at boot time this bit is
cleared, the processor boots in real mode. Real mode means,